Taoyuan, Taiwan

Shin-Yu Nieh

This inventor holds 6 USPTO granted patents and 4 published patent applications. Top assignee: Nan Ya Technology Corporation. Active years: 2010-2018.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Shin-Yu Nieh. Retrieved from https://idiyas.com/inventor/shin-yu-nieh

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 6 

% Patents Active = 100.0

Average Co-Inventor Count = 2.1

ph-index = 2

Forward Citations = 7(Granted Patents)


Location History:

  • Taoyuan County, TW (2011 - 2012)
  • Taipei, TW (2010 - 2014)
  • Taoyuan, TW (2018)

Company Filing History:


Years Active: 2010-2018

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6 patents (USPTO):Explore Patents

Title: Innovations by Shin-Yu Nieh

Introduction

Shin-Yu Nieh is a prominent inventor based in Taoyuan, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 6 patents. His work focuses on innovative methods for fabricating semiconductor devices, which are crucial for modern electronics.

Latest Patents

One of his latest patents is titled "Method of manufacturing a PMOS transistor comprising a dual work function metal gate." This invention provides a comprehensive method for fabricating a semiconductor device. The process includes forming a dummy gate on a substrate, creating an inter-layer dielectric layer (ILD) on the dummy gate and substrate, and forming a metal layer on the upper surface of the dummy gate. The method continues with the removal of the dummy gate to create a trench in the ILD, followed by the conformal formation of a gate dielectric layer in the trench. A first conductive type metal layer is then formed on the gate dielectric layer, which is subsequently anisotropically etched to create a gap in the ILD, filled with a second conductive type metal layer.

Another notable patent is the "Method of fabricating semiconductor device." This method describes a process that begins with providing a substrate with first and second areas. A first patterned mask layer is formed over the substrate, featuring at least one first opening in the first area and at least one second opening in the second area. The first opening is smaller than the second. The substrate is then partially removed using the first patterned mask layer as a mask, resulting in the formation of first and second trenches in the substrate. A first dielectric layer is created in the trenches, followed by the formation of a conductive structure on the first dielectric layer along the sidewalls of each trench.

Career Highlights

Shin-Yu Nieh is currently employed at Nan Ya Technology Corporation, where he continues to innovate in semiconductor technology. His work has been instrumental in advancing the capabilities of semiconductor devices, which are essential for various electronic applications.

Collaborations

He has collaborated with notable colleagues, including Jei-Cheng Huang and Tieh-Chiang Wu, contributing to the development of cutting-edge technologies in the semiconductor field.

Conclusion

Shin-Yu Nieh's contributions to semiconductor technology through his innovative patents highlight his expertise and dedication to advancing the industry. His work continues to influence the

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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