Nan Ya Technology Corporation

Shin-Yu Nieh

Tieh-Chiang Wu

Wei-Ming Liao

Hai-Han Hung

Jei-Cheng Huang

Chung-Yen Chou

Hsiu-Chun Lee

Teng-Wang Huang

Cheng-Shun Chen

Shuo-Che Chang

Hui-Lan Chang

The invention provides a method for fabricating a semiconductor device, including: forming a dummy gate on a substrate, forming an inter-layer dielectric layer (ILD) on the dummy gate and the substrate, forming a metal layer on the upper surface of the dummy gate, removing the dummy gate to form a trench in the inter-layer dielectric layer (ILD), conformally forming a gate dielectric layer in the trench, conformally forming a first conductive type metal layer on the gate dielectric layer, anisotropic etching the first conductive type metal layer and the gate dielectric layer over the metal layer to form a gap in the inter-layer dielectric layer (ILD), and filling a second conductive type metal layer in the gap.

Method of manufacturing a PMOS transistor comprising a dual work function metal gate

A method of fabricating a semiconductor device is described. A substrate having first and second areas is provided. A first patterned mask layer having at least one first opening in the first area and at least one second opening in the second area is formed over the substrate, wherein the first opening is smaller than the second opening. A portion of the substrate is removed with the first patterned mask layer as a mask to form first and second trenches respectively in the substrate in the first and second areas, wherein the width and the depth of the first trench are less than those of the second trench. A first dielectric layer is formed at least in the first and second trenches. A conductive structure is formed on the first dielectric layer on at least a portion of the sidewall of each of the first and second trenches.

Method of fabricating semiconductor device

The invention provides a method for forming a stack capacitor of a memory device, including providing a substrate, forming a patterned sacrificial layer with a plurality of first openings over the substrate, conformally forming a first conductive layer on the patterned sacrificial layer and in the first openings, forming a second conductive layer on the first conductive layer to seal the first openings with a void formed therein, removing a portion of the first and second conductive layers to expose the patterned sacrificial layer, and removing at least a portion of the patterned sacrificial layer to form bottom cell plates.

Stack capacitor of memory device and fabrication method thereof

A method for seamless gap filling is provided, including providing a semiconductor structure with a device layer having a gap therein, wherein the gap has an aspect ratio greater than 4. A liner layer is formed over the device layer exposed by the gap. A first un-doped oxide layer is formed over the liner layer in the gap. A doped oxide layer is formed over the first undoped oxide layer in the gap. A second un-doped oxide layer is formed over the doped oxide layer in the gap to fill the gap. An annealing process is performed on the second un-doped oxide layer, the doped oxide layer, and the first un-doped oxide to form a seamless oxide layer in the gap, wherein the seamless oxide layer has an interior doped region.

Methods of seamless gap filling

The invention provides a method for forming a deep trench in a substrate. A sacrificial layer and a liner layer are first used to define the deep trench pattern. The sacrificial layer is then replaced with a silicon glass layer. A thick mask layer includes the silicon glass layer, the liner layer and a silicon nitride layer is formed on the substrate. Through an opening of the thick mask layer, a deep trench is etched into the substrate.

Growing community of inventors

Taoyuan County, Taiwan

Shin-Yu Nieh