The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 29, 2018

Filed:

Jun. 30, 2016
Applicant:

Nanya Technology Corp., Taoyuan, TW;

Inventors:

Shin-Yu Nieh, Taoyuan, TW;

Tieh-Chiang Wu, Taoyuan, TW;

Wei-Ming Liao, Taoyuan, TW;

Jei-Cheng Huang, Taoyuan, TW;

Hai-Han Hung, Taoyuan, TW;

Hsiu-Chun Lee, Taoyuan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4966 (2013.01); H01L 21/28079 (2013.01); H01L 21/28088 (2013.01); H01L 21/28105 (2013.01); H01L 29/4958 (2013.01); H01L 29/4983 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/66553 (2013.01); H01L 29/495 (2013.01); H01L 29/518 (2013.01);
Abstract

The invention provides a method for fabricating a semiconductor device, including: forming a dummy gate on a substrate, forming an inter-layer dielectric layer (ILD) on the dummy gate and the substrate, forming a metal layer on the upper surface of the dummy gate, removing the dummy gate to form a trench in the inter-layer dielectric layer (ILD), conformally forming a gate dielectric layer in the trench, conformally forming a first conductive type metal layer on the gate dielectric layer, anisotropic etching the first conductive type metal layer and the gate dielectric layer over the metal layer to form a gap in the inter-layer dielectric layer (ILD), and filling a second conductive type metal layer in the gap.


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