Taipei, Taiwan

Jei-Cheng Huang

This inventor holds 5 USPTO granted patents and 3 published patent applications. Top assignee: Nan Ya Technology Corporation. Active years: 2014-2022.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Jei-Cheng Huang. Retrieved from https://idiyas.com/inventor/jei-cheng-huang

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 5 

% Patents Active = 100.0

Average Co-Inventor Count = 2.1

ph-index = 1

Forward Citations = 3(Granted Patents)


Location History:

  • Taoyuan, TW (2018)
  • New Taipei, TW (2014 - 2022)

Company Filing History:


Years Active: 2014-2022

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5 patents (USPTO):Explore Patents

Title: Innovations of Jei-Cheng Huang

Introduction

Jei-Cheng Huang is a prominent inventor based in Taipei, Taiwan. He has made significant contributions to the field of semiconductor technology, holding a total of 5 patents. His work focuses on enhancing the reliability and performance of metal-oxide-semiconductor field-effect transistors (MOSFETs).

Latest Patents

One of his latest patents is a "Method for aging simulation model establishment." This method involves several operations, including providing a planar p-type metal-oxide-semiconductor field-effect transistor (pMOSFET) with a source and a drain. It measures the first reliability degradation data of the pMOSFET and selects a model with parameters related to hot carrier induced punch-through (HEIP). The modeling parameters include hot carrier injection (HCI) parameters that help fix a simulated current relation between the source and the drain. The method constructs the modeling parameters by multiplying aging parameters with corresponding flags. It performs a simulation of the pMOSFET to obtain second reliability degradation data and updates the aging parameters if the first and second reliability degradation data do not match. The aging parameters are collected when the data matches, establishing the aging simulation model for the pMOSFET.

Another notable patent is the "Standard cell establishment method." This method includes setting a first implant split case and obtaining a plurality of characteristic parameters based on that case. It applies these parameters to a device delay metric to obtain a speed parameter. If the speed parameter is better than a previous one, it optimizes a channel parameter and establishes a standard cell if the optimization is successful.

Career Highlights

Jei-Cheng Huang is currently employed at Nan Ya Technology Corporation, where he continues to innovate in semiconductor technology. His work has significantly impacted the reliability and efficiency of electronic devices.

Collaborations

He has collaborated with notable coworkers, including Tieh-Chiang Wu and Wei-Ming Liao, contributing to various projects and advancements in their field.

Conclusion

Jei-Cheng Huang's contributions to semiconductor technology through his innovative patents demonstrate his expertise and commitment to advancing the industry. His work continues to influence the development of reliable electronic components.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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