Nan Ya Technology Corporation

Jei-Cheng Huang

Tieh-Chiang Wu

Wei-Ming Liao

Shin-Yu Nieh

Jhen-Yu Tsai

Tsung-Yu Tsai

Hai-Han Hung

Hsiu-Chun Lee

A method for aging simulation model establishment includes following operations. Provide a planar p-type metal-oxide-semiconductor field-effect transistor (pMOSFET) having a source and a drain. Measure a first reliability degradation data of the pMOSFET. Select a model for the pMOSFET with modeling parameters related to hot carrier induced punch-through (HEIP). The modeling parameters comprise hot carrier injection (HCI) parameters used to fix a simulated current relation between the source and the drain. Construct the modeling parameters by aging parameters multiplied corresponding flags. Perform a simulation of the pMOSFET with the model to have a second reliability degradation data. Update the aging parameters and re-performing the simulation if the first reliability degradation data and second reliability degradation data are not matched. Collect the aging parameters when the first reliability degradation data and the second reliability degradation data are matched to establish the aging simulation model for the pMOSFET.

Method for aging simulation model establishment

A standard cell establishment method is disclosed. The standard cell establishment method includes the following operations: setting a first implant split case; obtaining a plurality of characteristic parameters according to the first implant split case; applying the plurality of characteristic parameters to a device delay metric so as to obtain a speed parameter; optimizing a channel parameter if the speed parameter is better than a previous speed parameter; and establishing a standard cell if the channel parameter is optimized successfully.

Standard cell establishment method

The present disclosure provides a transistor device and a semiconductor layout structure. The transistor device includes a substrate including at least one active region, an isolation structure surrounding the active region, a gate structure disposed over the substrate, and a source/drain region disposed at two opposite sides of the gate structure. The gate structure includes a first portion extending along a first direction and a second portion extending along a second direction perpendicular to the first direction. The first portion of the gate structure overlaps a first boundary between the active region and the isolation structure.

Transistor device and semiconductor layout structure

The invention provides a method for fabricating a semiconductor device, including: forming a dummy gate on a substrate, forming an inter-layer dielectric layer (ILD) on the dummy gate and the substrate, forming a metal layer on the upper surface of the dummy gate, removing the dummy gate to form a trench in the inter-layer dielectric layer (ILD), conformally forming a gate dielectric layer in the trench, conformally forming a first conductive type metal layer on the gate dielectric layer, anisotropic etching the first conductive type metal layer and the gate dielectric layer over the metal layer to form a gap in the inter-layer dielectric layer (ILD), and filling a second conductive type metal layer in the gap.

Method of manufacturing a PMOS transistor comprising a dual work function metal gate

A method of fabricating a semiconductor device is described. A substrate having first and second areas is provided. A first patterned mask layer having at least one first opening in the first area and at least one second opening in the second area is formed over the substrate, wherein the first opening is smaller than the second opening. A portion of the substrate is removed with the first patterned mask layer as a mask to form first and second trenches respectively in the substrate in the first and second areas, wherein the width and the depth of the first trench are less than those of the second trench. A first dielectric layer is formed at least in the first and second trenches. A conductive structure is formed on the first dielectric layer on at least a portion of the sidewall of each of the first and second trenches.

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Taipei, Taiwan

Jei-Cheng Huang