The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 27, 2022
Filed:
Mar. 16, 2020
Nanya Technology Corporation, New Taipei, TW;
Jei-Cheng Huang, New Taipei, TW;
NANYA TECHNOLOGY CORPORATION, New Taipei, TW;
Abstract
A method for aging simulation model establishment includes following operations. Provide a planar p-type metal-oxide-semiconductor field-effect transistor (pMOSFET) having a source and a drain. Measure a first reliability degradation data of the pMOSFET. Select a model for the pMOSFET with modeling parameters related to hot carrier induced punch-through (HEIP). The modeling parameters comprise hot carrier injection (HCI) parameters used to fix a simulated current relation between the source and the drain. Construct the modeling parameters by aging parameters multiplied corresponding flags. Perform a simulation of the pMOSFET with the model to have a second reliability degradation data. Update the aging parameters and re-performing the simulation if the first reliability degradation data and second reliability degradation data are not matched. Collect the aging parameters when the first reliability degradation data and the second reliability degradation data are matched to establish the aging simulation model for the pMOSFET.