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For the Inventor, By the Inventor

San Jose, CA, United States of America

Ravi Sundaresan

This inventor holds 29 USPTO granted patents and 1 EPO patent, primarily in CMOS Technology. Top assignees: Chartered Semiconductor Manufacturing Ltd (Corporation), Stmicroelectronics Gmbh. Active years: 1997-2004.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Ravi Sundaresan. Retrieved from https://idiyas.com/inventor/ravi-sundaresan

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 29

% Patents Active = 65.5


Average Co-Inventor Count = 5.9

ph-index = 15

Forward Citations = 870(Granted Patents)


Location History:

  • Singapore, SG (1997 - 1998)
  • San Jose, CA (US) (2001 - 2004)
  • Plano, TX (US) (2001 - 2004)

Company Filing History:

goldMedal27 out of 962 
 
Chartered Semiconductor Manufacturing Ltd (Corporation)
 patents
silverMedal2 out of 2,891 
 
Stmicroelectronics Gmbh
 patents

Years Active: 1997-2004

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Areas of Expertise:
CMOS Inverter
Vertical Transistor
Gate Dielectric
High Mobility
Low Capacitance
Self-Aligned
STI Structure
Selectively Epitaxial
Trench Formation
Transistor Fabrication
Microtrench
Hydrogen Rich Nitride
29 patents (USPTO):Explore Patents
1. 6759717 - CMOS integrated circuit device with LDD n-channel transistor and non-LDD p-channel transistor (2004-07-06),
2. 6747314 - Method to form a self-aligned CMOS inverter using vertical device integration (2004-06-08),
3. 6709934 - Method for forming variable-K gate dielectric (2004-03-23),
4. 6544824 - Method to form a vertical transistor by first forming a gate/spacer stack, then using selective epitaxy to form source, drain and channel (2003-04-08),
5. 6541327 - Method to form self-aligned source/drain CMOS device on insulated staircase oxide (2003-04-01),
6. 6511884 - Method to form and/or isolate vertical transistors (2003-01-28),
7. 6475916 - Method of patterning gate electrode with ultra-thin gate dielectric (2002-11-05),
8. 6468877 - Method to form an air-gap under the edges of a gate electrode by using disposable spacer/liner (2002-10-22),
9. 6461900 - Method to form a self-aligned CMOS inverter using vertical device integration (2002-10-08),
10. 6461887 - Method to form an inverted staircase STI structure by etch-deposition-etch and selective epitaxial growth (2002-10-08),
11. 6455377 - Method to form very high mobility vertical channel transistor by selective deposition of SiGe or multi-quantum wells (MQWs) (2002-09-24),
12. 6440800 - Method to form a vertical transistor by selective epitaxial growth and delta doped silicon layers (2002-08-27),
13. 6436774 - Method for forming variable-K gate dielectric (2002-08-20),
14. 6436770 - Method to control the channel length of a vertical transistor by first forming channel using selective epi and source/drain using implantation (2002-08-20),
15. 6417056 - Method to form low-overlap-capacitance transistors by forming microtrench at the gate edge (2002-07-09),

Title: Innovations and Contributions of Ravi Sundaresan

Introduction

Ravi Sundaresan, based in San Jose, California, is a prominent inventor with an impressive portfolio of 29 patents. His contributions to the field of integrated circuits have significantly advanced technology, particularly in the design and fabrication of CMOS devices.

Latest Patents

Among Sundaresan's latest innovations is a patent for a CMOS integrated circuit device that incorporates a lightly doped drain (LDD) n-channel transistor along with a non-LDD p-channel transistor. This method details a sophisticated technique for fabricating integrated circuits where LDD regions for the n-channel transistors are self-aligned to gate electrodes. It also outlines the process of forming multiple oxide layers to create sidewall spacers and low resistivity regions, enhancing the performance of the integrated circuit.

Another noteworthy patent by Sundaresan outlines a method for forming a self-aligned CMOS inverter through vertical device integration. This innovative approach enables the creation of closely spaced, vertical NMOS and PMOS transistors in integrated circuits, optimizing their performance by utilizing selective ion implantation techniques and sophisticated layering of silicon and oxide materials.

Career Highlights

Sundaresan has collaborated with renowned companies including Chartered Semiconductor Manufacturing Ltd and STMicroelectronics GmbH, where he contributed to groundbreaking advancements in semiconductor technology. His work at these leading firms has underscored his role as a key player in the development of cutting-edge integrated circuit technologies.

Collaborations

Throughout his career, Sundaresan has worked alongside talented professionals such as Lap Chan and Yang Pan. These collaborations have fostered an environment of innovation and excellence, further enhancing the quality of the projects he has been involved in.

Conclusion

Ravi Sundaresan's contributions to the field of integrated circuits through his extensive patent portfolio reflect his commitment to advancing technology. His innovative methods for fabricating CMOS devices not only demonstrate his technical expertise but also pave the way for future advancements in semiconductor technology.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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