Rahul M Rao

This inventor holds 19 USPTO granted patents and 5 published patent applications, primarily in Memory Circuit Design. Top assignee: International Business Machines Corporation. Active years: 2004-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Rahul M Rao. Retrieved from https://idiyas.com/inventor/rahul-m-rao

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 19 (Patent Applications = 5)

% Patents Active = 21.1

Average Co-Inventor Count = 3.3

ph-index = 5

Forward Citations = 104(Granted Patents)

Location History:

Ann Arbor, MI (US) (2004 - 2006)
Elmsford, NY (US) (2008 - 2013)
Austin, TX (US) (2009 - 2015)

Company Filing History:

19 out of 166,425

International Business Machines Corporation

patents

Years Active: 2004-2026

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Areas of Expertise:

Memory Elements

Degradation Estimation

Transistor Variability

Static Random Access Memory

Logic Functions

Negative Bias Temperature Instability

Write Stability

Integrated Circuits

Electronic Circuits

Power Consumption

Gate Leakage

Bus Circuit

19 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 12711296 - SCAN CHAIN OPTIMIZATION UTILIZING CONSTRAINED SINGLE LINKAGE CLUSTERING (2026-08-18),

2. 9064071 - Usage-based temporal degradation estimation for memory elements (2015-06-23),

3. 9058448 - Usage-based temporal degradation estimation for memory elements (2015-06-16),

4. 8966420 - Estimating delay deterioration due to device degradation in integrated circuits (2015-02-24),

5. 8526219 - Enhanced static random access memory stability using asymmetric access transistors and design structure for same (2013-09-03),

6. 8493774 - Performing logic functions on more than one memory cell within an array of memory cells (2013-07-23),

7. 8456247 - Monitoring negative bias temperature instability (NBTI) and/or positive bias temperature instability (PBTI) (2013-06-04),

8. 8139400 - Enhanced static random access memory stability using asymmetric access transistors and design structure for same (2012-03-20),

9. 8004305 - Electronic circuit for measurement of transistor variability and the like (2011-08-23),

10. 7882370 - Static pulsed bus circuit and method having dynamic power supply rail selection (2011-02-01),

11. 7764080 - Methods of operating an electronic circuit for measurement of transistor variability and the like (2010-07-27),

12. 7746709 - Memory circuit with decoupled read and write bit lines and improved write stability (2010-06-29),

13. 7642864 - Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect (2010-01-05),

14. 7550987 - Method and circuit for measuring operating and leakage current of individual blocks within an array of test circuit blocks (2009-06-23),

15. 7548822 - Apparatus and method for determining the slew rate of a signal produced by an integrated circuit (2009-06-16),

Title: Innovations of Rahul M Rao

Introduction

Rahul M Rao is a prominent inventor based in Elmsford, NY (US). He has made significant contributions to the field of memory elements and transistor technology. With a total of 19 patents to his name, his work has had a substantial impact on the industry.

Latest Patents

One of his latest patents is titled "Usage-based temporal degradation estimation for memory elements." This patent discloses methods and systems for computing threshold voltage degradation of transistors in an array of memory cells. In accordance with one method, a process that models an expected usage of the array is selected. A hardware processor can run the process to populate the array with data over time to simulate the expected usage of the array. The method further includes compiling data that detail different durations at which each of the memory cells in the array stores 1 or at which each of the memory cells in the array stores 0. For each separate grouping of memory cells that share a common duration of the different compiled durations, a threshold voltage degradation is determined for each transistor in the corresponding grouping of cells based on at least one biased temperature instability model.

Career Highlights

Rahul M Rao is currently employed at International Business Machines Corporation, commonly known as IBM. His work at IBM has allowed him to explore innovative solutions in the field of memory technology and transistor performance.

Collaborations

Some of his notable coworkers include Jae-Joon Kim and Aditya Bansal. Their collaborative efforts contribute to the advancement of technology in their respective fields.

Conclusion

Rahul M Rao's contributions to the field of memory elements and transistors demonstrate his innovative spirit and dedication to advancing technology. His patents reflect a deep understanding of the complexities involved in memory technology, making him a valuable asset to the industry.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

5 patents pending: