The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 16, 2015

Filed:

Sep. 13, 2012
Applicants:

Aditya Bansal, White Plains, NY (US);

Jae-joon Kim, Old Tappan, NJ (US);

Rahul M. Rao, Austin, TX (US);

Inventors:

Aditya Bansal, White Plains, NY (US);

Jae-Joon Kim, Old Tappan, NJ (US);

Rahul M. Rao, Austin, TX (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/10 (2006.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5036 (2013.01); G06F 2217/76 (2013.01);
Abstract

Methods and systems for computing threshold voltage degradation of transistors in an array of memory cells are disclosed. In accordance with one method, a process that models an expected usage of the array is selected. In addition, a hardware processor can run the process to populate the array with data over time to simulate the expected usage of the array. The method further includes compiling data that detail different durations at which each of the memory cells in the array stores 1 or at which each of the memory cells in the array stores 0. For each separate grouping of memory cells that share a common duration of the different compiled durations, a threshold voltage degradation is determined for each transistor in the corresponding grouping of cells based on at least one biased temperature instability model.


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