Performing logic functions on more than one memory cell within an array of memory cells

Abstract

A circuit structure is provided for performing a logic function within a memory. A plurality of read word line transistors are provided that receive a read word line signal and, upon receiving the read word line signal, the plurality of read word line transistors provide a path from a plurality of bit-line transistors associated with a plurality of physically adjacent memory cells to a read bit-line. In response to an associated memory cell within the memory storing a first value, each of the plurality of read bit-line transistors turns on and provides a path to ground thereby causing a first output value to be output on the read bit-line. In response to all of the plurality of memory cells storing a second value, the plurality of read bit-line transistors turn off thereby preventing a path to ground and a second output value is output on the read bit-line.