The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2015
Filed:
Sep. 12, 2012
Aditya Bansal, White Plains, NY (US);
Jae-joon Kim, Yorktown Heights, NJ (US);
Rahul M. Rao, Austin, TX (US);
Aditya Bansal, White Plains, NY (US);
Jae-Joon Kim, Yorktown Heights, NJ (US);
Rahul M. Rao, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for estimating delay deterioration in an integrated circuit comprising estimating degradation in at least one characteristic of each device defined within the integrated circuit using voltages and logic values monitored during a simulation of the digital circuit. Generating an end-of-life netlist in which the at least one device characteristic of each device has been modified to reflect the estimated degradation or estimating a change in timing delay of each device directly from the estimated degradation of the at least one characteristic of each device. A timing analysis is performed using the estimated change in timing delay of each device to determine circuit path delays. The timing analysis is static or statistical.