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For the Inventor, By the Inventor

Chandler, AZ, United States of America

Purushotham Kaushik Muthur Srinath

USPTO Granted Patents = 14 

Average Co-Inventor Count = 4.5

ph-index = 2

Forward Citations = 10(Granted Patents)


Company Filing History:

goldMedal14 out of 54,664 
 
Intel Corporation
 patents

Years Active: 2015-2025

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14 patents (USPTO):
1. 12417958 - Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and PoP adhesive keep out zone (2025-09-16),
2. 12406906 - Through mold interconnect drill feature (2025-09-02),
3. 12394773 - Laser ablation-based surface property modification and contamination removal (2025-08-19),
4. 12362340 - Laser ablation-based surface property modification and contamination removal (2025-07-15),
5. 12347743 - Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and pop adhesive keep out zone (2025-07-01),
6. 12315777 - Microelectronics package comprising a package-on-package (POP) architecture with inkjet barrier material for controlling bondline thickness and POP adhesive keep out zone (2025-05-27),
7. 11705383 - Through mold interconnect drill feature (2023-07-18),
8. 11551956 - Method and device for failure analysis using RF-based thermometry (2023-01-10),
9. 11476120 - Method of sample preparation using dual ion beam trenching (2022-10-18),
10. 10607909 - Systems, methods, and apparatuses for implementing a thermal solution for 3D packaging (2020-03-31),
11. 10361167 - Electronic assembly using bismuth-rich solder (2019-07-23),
12. 9625256 - Device, system and method for alignment of an integrated circuit assembly (2017-04-18),
13. 9230833 - Methods to prevent filler entrapment in microelectronic device to microelectronic substrate interconnection structures (2016-01-05),
14. 8999765 - Methods to prevent filler entrapment in microelectronic device to microelectronic substrate interconnection structures (2015-04-07),

Title: Purushotham Kaushik Muthur Srinath: Pioneering Innovations in Technology

Introduction:

Purushotham Kaushik Muthur Srinath, a visionary inventor based in Chandler, AZ, is setting new standards in the world of technology through his dedication to innovation and technological advancement. With a remarkable portfolio of 8 patents, his contributions are revolutionizing the landscape of electronic packaging and failure analysis methodologies.

Latest Patents:

Srinath's latest patents showcase his ingenuity and expertise in the field of electronics. "Through Mold Interconnect Drill Feature" focuses on enhancing electronic packages by introducing innovative mold layers and through mold interconnects. Meanwhile, "Method and Device for Failure Analysis using RF-based Thermometry" presents a cutting-edge system for detecting and locating defects in semiconductor packaging architectures using RF signals.

Career Highlights:

Srinath's professional journey is marked by his association with Intel Corporation, a global leader in semiconductor manufacturing. His role at Intel has provided him with a platform to translate his inventive ideas into impactful technological solutions, further solidifying his reputation as a trailblazer in the industry.

Collaborations:

In his pursuit of excellence, Srinath has collaborated with esteemed colleagues such as Deepak Goyal and Manish Dubey. Together, they have synergized their expertise to drive innovation, resulting in collaborative projects that push the boundaries of technological possibilities.

Conclusion:

Purushotham Kaushik Muthur Srinath's unwavering commitment to pushing technological boundaries and his remarkable track record of innovation serve as a beacon of inspiration for aspiring inventors worldwide. His work not only shapes the future of technology but also underscores the transformative power of innovation in driving progress and advancement in the modern era.

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