The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 27, 2025

Filed:

Aug. 30, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Elizabeth Nofen, Phoenix, AZ (US);

Shripad Gokhale, Gilbert, AZ (US);

Nick Ross, Chandler, AZ (US);

Amram Eitan, Scottsdale, AZ (US);

Nisha Ananthakrishnan, Chandler, AZ (US);

Robert M. Nickerson, Chandler, AZ (US);

Purushotham Kaushik Muthur Srinath, Chandler, AZ (US);

Yang Guo, Chandler, AZ (US);

John C. Decker, Tempe, AZ (US);

Hsin-Yu Li, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/373 (2006.01); H01L 21/02 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/373 (2013.01); H01L 21/02288 (2013.01); H01L 21/565 (2013.01); H01L 21/76816 (2013.01); H01L 23/481 (2013.01);
Abstract

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.


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