The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2020
Filed:
Apr. 02, 2016
Intel Corporation, Santa Clara, CA (US);
Purushotham Kaushik Muthur Srinath, Chandler, AZ (US);
Pramod Malatkar, Chandler, AZ (US);
Sairam Agraharam, Chandler, AZ (US);
Chandra M. Jha, Tempe, AZ (US);
Arnab Choudhury, Chandler, AZ (US);
Nachiket R. Raravikar, Gilbert, AZ (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces therein; a first layer functional silicon die electrically interfaced to the electrical traces of the substrate layer, the first layer functional silicon die having a first thermal pad integrated thereupon; a second layer functional silicon die positioned above the first layer functional silicon die, the second layer functional silicon die having a second thermal pad integrated thereupon; and a conductivity layer positioned between the first layer functional silicon die and the second layer functional silicon die, wherein the conductivity layer is to: (i) electrically join the second layer functional silicon die to the first layer functional silicon die and (ii) bond the first thermal pad of the first layer functional silicon die to the second thermal pad of the second layer functional silicon die via solder. Other related embodiments are disclosed.