Intel Corporation

Purushotham Kaushik Muthur Srinath

Robert M Nickerson

Shripad Gokhale

Deepak Goyal

Nisha Ananthakrishnan

Amram Eitan

Elizabeth Nofen

Hsin-Yu Li

John Decker

Yang Guo

Nick Ross

Rajendra C Dias

Manish Dubey

Yiqun Bai

Arjun Krishnan

Yonghao Xiu

Rees Winters

Andrew V Mazur

Denis Myasishchev

Nachiket R Raravikar

Sairam Agraharam

Chandra Mohan Jha

Pramod Malatkar

Phillip C Miller

Arnab Choudhury

Mario Pacheco

Pilin Liu

Richard Kenneth Brewer

Chandrashekara Shashank Kaira

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and PoP adhesive keep out zone

Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and a mold layer over the package substrate and around the first die. In an embodiment, the electronic package further comprises a through mold opening through the mold layer, and a through mold interconnect (TMI) in the through mold opening, wherein a center of the TMI is offset from a center of the through mold opening.

Through mold interconnect drill feature

Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a mold layer and a die embedded in the mold layer. In an embodiment the electronic package further comprises a solder resist with a first surface over the mold layer and a second surface opposite from the first surface. In an embodiment, the second surface comprises a first cavity into the solder resist.

Laser ablation-based surface property modification and contamination removal

Microelectronics package comprising a package-on-package (PoP) architecture with inkjet barrier material for controlling bondline thickness and pop adhesive keep out zone

Microelectronics package comprising a package-on-package (POP) architecture with inkjet barrier material for controlling bondline thickness and POP adhesive keep out zone

According to the various examples, a fully integrated system and method for failure analysis using RF-based thermometry enable the detection and location of defects and failures in complex semiconductor packaging architectures. The system provides synchronous amplified RF signals to generate unique thermal signatures at defect locations based on dielectric relaxation loss and heating.

Method and device for failure analysis using RF-based thermometry

Systems and methods of sample preparation using dual ion beam trenching are described. In an example, an inside of a semiconductor package is non-destructively imaged to determine a region of interest (ROI). A mask is positioned over the semiconductor package, and a mask window is aligned with the ROI. A first ion beam and a second ion beam are swept, simultaneously or sequentially, along an edge of the mask window to trench the semiconductor package and to expose the ROI for analysis.

Method of sample preparation using dual ion beam trenching

In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a thermal solution for 3D packaging. For instance, in accordance with one embodiment, there is an apparatus having therein: a substrate layer having electrical traces therein; a first layer functional silicon die electrically interfaced to the electrical traces of the substrate layer, the first layer functional silicon die having a first thermal pad integrated thereupon; a second layer functional silicon die positioned above the first layer functional silicon die, the second layer functional silicon die having a second thermal pad integrated thereupon; and a conductivity layer positioned between the first layer functional silicon die and the second layer functional silicon die, wherein the conductivity layer is to: (i) electrically join the second layer functional silicon die to the first layer functional silicon die and (ii) bond the first thermal pad of the first layer functional silicon die to the second thermal pad of the second layer functional silicon die via solder. Other related embodiments are disclosed.

Systems, methods, and apparatuses for implementing a thermal solution for 3D packaging

Some forms relate to an electronic assembly includes a first substrate that has a copper pad mounted to the first substrate. The electronic assembly further includes a second substrate that includes a copper redistribution layer mounted on the second substrate. The electronic assembly further includes bismuth-rich solder that includes 10-40 w.t. % tin. The bismuth-rich solder is electrically engaged with the copper pad and the copper redistribution layer. In some forms, the copper redistribution layer is another copper pad. The first substrate may include a memory die and the second substrate may include a logic die. In other forms, the first and second substrates may be part of a variety of different electronic components. The types of electronic components that are associated with the first and second substrates will depend on part on the application where the electronic assembly is be utilized (among other factors).

Electronic assembly using bismuth-rich solder

Techniques and mechanisms for evaluating misalignment of circuit structures. In an embodiment, infrared (IR) radiation is variously focused on different planes of an assembly including an integrated circuit (IC) chip and a substrate that is to be coupled to, or that is coupled to, the IC chip. The cross-sectional planes include respective structures that variously reflect IR radiation. The reflected IR radiation is measured to create images each representing a corresponding cross-section of the assembly. In another embodiment, respective reference features of the images are identified and evaluated to determine whether a misalignment between the reference features satisfies one or more threshold test conditions.

Device, system and method for alignment of an integrated circuit assembly

Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particless within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.

Methods to prevent filler entrapment in microelectronic device to microelectronic substrate interconnection structures

Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particles within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.

Growing community of inventors

Chandler, AZ, United States of America

Purushotham Kaushik Muthur Srinath