Praveen K Parvathala

Title: Praveen K Parvathala: Innovator in Integrated Circuit Testing

Introduction

Praveen K Parvathala is a notable inventor based in Phoenix, AZ, who has made significant contributions to the field of integrated circuit testing. With a total of 7 patents to his name, he has developed innovative methods that enhance the efficiency and effectiveness of testing complex devices.

Latest Patents

One of his latest patents is titled "Enabling at speed application of test patterns associated with a wide tester interface on a low pin count tester." This invention allows for the application of test patterns at speed on low pin count testers, utilizing an integrated circuit that includes a processor core and a cache structure for storing test information. The multiplexer in this design plays a crucial role in providing the necessary signals to the processor core.

Another significant patent is the "Functional random instruction testing (FRIT) method for complex devices such as microprocessors." This method involves generating a FRIT kernel that includes a software built-in self-test engine. It is designed to execute a re-generative functional test of the device under test (DUT) and compares the results to expected outcomes to identify manufacturing defects.

Career Highlights

Praveen K Parvathala is currently employed at Intel Corporation, where he continues to push the boundaries of technology in integrated circuit testing. His work has been instrumental in developing methods that improve the reliability and performance of complex devices.

Collaborations

Throughout his career, Praveen has collaborated with talented individuals such as Kailasnath S Maneparambil and Fred Gruner, contributing to a dynamic work environment that fosters innovation.

Conclusion

Praveen K Parvathala's contributions to integrated circuit testing through his patents and work at Intel Corporation highlight his role as a leading inventor in the field. His innovative methods are paving the way for advancements in technology and testing methodologies.