The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 16, 1999

Filed:

Nov. 26, 1997
Applicant:
Inventors:

Praveen Parvathala, Phoenix, AZ (US);

Fred Gruner, Palo Alto, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 2231 ;
Abstract

A method and apparatus for using a test signal being computed by applying a combinational test pattern generation tool to a model of the apparatus in which at least one of an at least one sequential device is modelled as a non-sequential device, the apparatus having a first scan cell configured to receive the test signal and drive a first signal in response to a first clock phase; a sequential logic block having the at least one sequential device, the sequential logic block being configured to generate a second signal, at least one of the at least one sequential device being a non-scan cell.


Find Patent Forward Citations

Parvathala, Praveen. (1999). Method and apparatus for scan testing of multi-phase logic (U.S. Patent No. 5872795). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/5872795

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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