Redwood City, CA, United States of America

Paul A Clifton

USPTO Granted Patents = 57 

 

Average Co-Inventor Count = 2.2

ph-index = 11

Forward Citations = 271(Granted Patents)

Forward Citations (Not Self Cited) = 145(Dec 10, 2025)


Inventors with similar research interests:


Location History:

  • Menlo Park, CA (US) (2005 - 2012)
  • Mountain View, CA (US) (2008 - 2014)
  • Redwood City, CA (US) (2014 - 2024)
  • Palo Alto, CA (US) (2016 - 2024)

Company Filing History:


Years Active: 2005-2025

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Areas of Expertise:
Nanowire Transistor
SOI Wafers
Group IV Semiconductors
Strained Semiconductor
Photon Emission Devices
MIS Contact Structure
Elastic Edge Relaxation
Integrated Photonics
Field Effect Transistor
Biaxial Strained FET
Strain-Enhanced Silicon
Self-Aligned Source/Drain
57 patents (USPTO):Explore Patents

Title: Innovations of Paul A. Clifton in Nanotechnology

Introduction

Paul A. Clifton, an accomplished inventor based in Redwood City, CA, holds an impressive portfolio of 54 patents. His work primarily focuses on advancements in nanotechnology and semiconductor devices, showcasing his significant contributions to the field.

Latest Patents

Among his latest patents are two notable inventions:

1. **Nanowire Transistor with Source and Drain Induced by Electrical Contacts with Negative Schottky Barrier Height** - This innovative nanowire transistor features undoped source and drain regions that are electrically coupled with a channel region. The design includes a source stack, which is completely coaxially wrapped around the source region, featuring an interfacial layer and a source conductor. The unique aspect of this transistor is that it incorporates a negative Schottky barrier, effectively inducing a concentration of free charge carriers in the semiconductor source region.

2. **Strained Semiconductor Using Elastic Edge Relaxation of a Stressor Combined with Buried Insulating Layer** - This patent describes a Silicon-On-Insulator (SOI) wafer that contains a compressively stressed buried insulator structure. The stressed buried insulator is formed with multiple layers of silicon oxide and silicon nitride, where the silicon nitride layer is under compression. The invention aims to optimize MOS transistors via specific etching of isolation trenches that penetrate through the stressed buried insulator, inducing tensile stress in the overlying silicon active regions.

Career Highlights

Paul A. Clifton has worked with notable companies such as Acorn Technologies, Inc. and Acorn Semi, LLC. His expertise in semiconductor technologies has driven innovations that push the boundaries of what is possible within the industry. His extensive patent portfolio illustrates his dedication to advancing nanotechnologies and provides insight into the significant impact of his research.

Collaborations

Throughout his career, Clifton has collaborated with esteemed peers including Andreas Goebel and R. Stockton Gaines. These partnerships have played a crucial role in the development of his groundbreaking technologies and patents.

Conclusion

In summary, Paul A. Clifton's innovative contributions to the field of nanotechnology are evident through his extensive system of patents and collaborative efforts. His work continues to influence the evolving landscape of semiconductor technology, cementing his status as a leading inventor in this pivotal area of research.

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