The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2025
Filed:
Jun. 21, 2024
Applicant:
Acorn Semi, Llc, Palo Alto, CA (US);
Inventors:
Paul A. Clifton, Palo Alto, CA (US);
Andreas Goebel, Mountain View, CA (US);
Walter A. Harrison, Palo Alto, CA (US);
Assignee:
Acorn Semi, LLC, Palo Alto, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/67 (2025.01); B82Y 10/00 (2011.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 62/13 (2025.01); H10D 64/23 (2025.01); H10D 64/64 (2025.01);
U.S. Cl.
CPC ...
H10D 30/6713 (2025.01); B82Y 10/00 (2013.01); H10D 30/43 (2025.01); H10D 30/62 (2025.01); H10D 30/6211 (2025.01); H10D 30/6219 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 62/151 (2025.01); H10D 64/251 (2025.01); H10D 64/647 (2025.01);
Abstract
A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.