The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 26, 2025

Filed:

Sep. 11, 2023
Applicant:

Acorn Semi, Llc, Palo Alto, CA (US);

Inventors:

Paul A. Clifton, Palo Alto, CA (US);

Andreas Goebel, Mountain View, CA (US);

Assignee:

Acorn Semi, LLC, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 30/69 (2025.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01); H10D 86/00 (2025.01);
U.S. Cl.
CPC ...
H10D 30/798 (2025.01); H01L 21/02381 (2013.01); H01L 21/02532 (2013.01); H01L 21/76254 (2013.01); H01L 21/76283 (2013.01); H10D 30/751 (2025.01); H10D 30/792 (2025.01); H10D 30/795 (2025.01); H10D 30/797 (2025.01); H10D 62/115 (2025.01); H10D 62/314 (2025.01); H10D 86/201 (2025.01);
Abstract

A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.


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