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For the Inventor, By the Inventor

Santa Clara, CA, United States of America

Nadathur Rajagopalan Satish

This inventor holds 60 USPTO granted patents and 12 published patent applications and 11 EPO patents, primarily in Neural Network Optimization (CPC class G06F). Top assignee: Intel Corporation. Active years: 2012-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Nadathur Rajagopalan Satish. Retrieved from https://idiyas.com/inventor/nadathur-rajagopalan-satish

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank
USPTO Granted Patents = 60 

% Patents Active = 86.7

 

Average Co-Inventor Count = 9.5

ph-index = 6

Forward Citations = 147(Granted Patents)

Forward Citations (Not Self Cited) = 125(Dec 10, 2025)


Inventors with similar research interests:


Company Filing History:

goldMedal60 out of 56,394 
 
Intel Corporation
 patents

Years Active: 2012-2026

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Areas of Expertise:
Neural Network
Matrix Multiplication
Graphics Processing
Compute Optimization
Dynamic Precision
Machine Learning
Data Operations
Programmable Hardware
Autonomous Machines
Finite State Machine
Dynamic Training
Sparse Matrix
60 patents (USPTO):Explore Patents
1. 12547672 - Accelerator for sparse-dense matrix multiplication (2026-02-10),
2. 12536130 - Graphics processing integrated circuit package (2026-01-27),
3. 12499347 - Neural network scheduling mechanism (2025-12-16),
4. 12412086 - Neural network optimization mechanism (2025-09-09),
5. 12346798 - Dynamic precision for neural network compute operations (2025-07-01),
6. 12198221 - Compute optimization mechanism for deep neural networks (2025-01-14),
7. 12112397 - Programmable coarse grained and sparse matrix compute hardware with advanced scheduling (2024-10-08),
8. 12056788 - Compute optimization mechanism (2024-08-06),
9. 11922535 - Compute optimization mechanism for deep neural networks (2024-03-05),
10. 11829440 - Accelerator for sparse-dense matrix multiplication (2023-11-28),
11. 11809978 - Neural network scheduling mechanism (2023-11-07),
12. 11797837 - Dynamic distributed training of machine learning models (2023-10-24),
13. 11748606 - Dynamic precision for neural network compute operations (2023-09-05),
14. 11748298 - Graphics processing integrated circuit package (2023-09-05),
15. 11748106 - Data operations and finite state machine for machine learning via bypass of computational tasks based on frequently-used data values (2023-09-05),

Title: The Innovative Journey of Nadathur Rajagopalan Satish

Introduction: Nadathur Rajagopalan Satish, a pioneering inventor based in Santa Clara, CA, has made significant contributions to the world of technology through his groundbreaking innovations.

Latest Patents: Satish holds several patents in the field of semiconductor technology, including a recent patent for a novel method of enhancing chip performance through advanced cooling techniques.

Career Highlights: With a career spanning over two decades, Satish has worked with leading tech companies, driving innovation and pushing the boundaries of what is possible in the semiconductor industry. His expertise in chip design and optimization has earned him recognition as a thought leader in the field.

Collaborations: Throughout his career, Satish has collaborated with top engineers, researchers, and industry experts to develop cutting-edge solutions that have revolutionized the way we think about semiconductor technology. His collaborative spirit and passion for innovation continue to inspire others in the industry.

Conclusion: Nadathur Rajagopalan Satish's relentless pursuit of innovation and his commitment to pushing the boundaries of technology have solidified his position as a visionary inventor in the world of semiconductor technology. His contributions have not only shaped the industry but have also paved the way for future advancements in the field.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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