Intel Corporation

Nadathur Rajagopalan Satish

Farshad Akhbari

Altug Koker

Feng Chen

Dukhwan Kim

Narayan Srinivasa

Abhishek R Appu

Joydeep Ray

Eriko Nurvitadhi

Balaji Vembu

Kamal Sinha

Linda L Hurd

Justin E Gottschlich

Xiaoming Chen

Nicolas C Galoppo Von Borries

Sara S Baghsorkhi

Anbang Yao

Rajkishore Barik

Tsung-Han Lin

Michael S Strickland

Prasoonkumar Surti

Tatiana Shpeisman

Ping Tak Tang

Jeremy Bottleson

John Charles Weast

Ben J Ashbaugh

Travis T Schluessler

Liwei Ma

Subramaniam M Maiyuran

Vasanth Ranganathan

Sanjeev S Jahagirdar

Karthik Vaidyanathan

Adam T Lake

John H Feit

Jeffery S Boles

Devan Burke

Wenyin Fu

Josh B Mastronarde

Mike B Macpherson

Changkyu Kim

Elmoustapha Ould-Ahmed-Vall

Chandrasekaran Sakthivel

Jatin Chhugani

Kevin Nealis

Christopher J Hughes

Victor W Lee

Daehyun Kim

Barath Lakshmanan

Yen-Kuang Chen

Kenneth J Janik

Alexey Suprun

Anthony-Trung D Nguyen

Srinivasan Narayanamoorthy

Narayan Biswal

Stanley J Baran

Gokcen Cilingir

Nilesh V Shah

Barnan Das

Archie Sharma

Mayuresh M Varerkar

Sherine Abdelhak

Jingyi Jin

Sachin B Godse

Jason D Sewall

Ankur N Shah

Sanjeev Kumar

Mike MacPherson

Deborah T Marr

Jonathan Kennedy

Jong Soo Park

Sheng C Li

Mikhail Smelyanskiy

Asit K Mishra

Michael A Anderson

Xiangyao Yu

Changkyu Ck Kim

Narayanan Sundaram

Bryan Catanzaro

Mostofa Ali Patwary

Michael Strikland

An apparatus to facilitate optimization of a neural network (NN) is disclosed. The apparatus includes optimization logic to define a NN topology having one or more macro layers, adjust the one or more macro layers to adapt to input and output components of the NN and train the NN based on the one or more macro layers.

Neural network optimization mechanism

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Dynamic precision for neural network compute operations

Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

Compute optimization mechanism for deep neural networks

One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.

Programmable coarse grained and sparse matrix compute hardware with advanced scheduling

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core including mixed-precision execution circuitry to execute one or more of the mixed-precision instructions to perform a mixed-precision dot-product operation comprising to perform a set of multiply and accumulate operations.

Compute optimization mechanism

Disclosed embodiments relate to an accelerator for sparse-dense matrix instructions. In one example, a processor to execute a sparse-dense matrix multiplication instruction, includes fetch circuitry to fetch the sparse-dense matrix multiplication instruction having fields to specify an opcode, a dense output matrix, a dense source matrix, and a sparse source matrix having a sparsity of non-zero elements, the sparsity being less than one, decode circuitry to decode the fetched sparse-dense matrix multiplication instruction, execution circuitry to execute the decoded sparse-dense matrix multiplication instruction to, for each non-zero element at row M and column K of the specified sparse source matrix generate a product of the non-zero element and each corresponding dense element at row K and column N of the specified dense source matrix, and generate an accumulated sum of each generated product and a previous value of a corresponding output element at row M and column N of the specified dense output matrix.

Accelerator for sparse-dense matrix multiplication

An apparatus to facilitate workload scheduling is disclosed. The apparatus includes one or more clients, one or more processing units to processes workloads received from the one or more clients, including hardware resources and scheduling logic to schedule direct access of the hardware resources to the one or more clients to process the workloads.

Neural network scheduling mechanism

In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

Dynamic distributed training of machine learning models

A mechanism is described for facilitating fast data operations and for facilitating a finite state machine for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting input data to be used in computational tasks by a computation component of a processor including a graphics processor. The method may further include determining one or more frequently-used data values (FDVs) from the data, and pushing the one or more frequent data values to bypass the computational tasks.

Data operations and finite state machine for machine learning via bypass of computational tasks based on frequently-used data values

An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

Graphics processing integrated circuit package

One embodiment provides for a compute apparatus to perform machine learning operations, the compute apparatus comprising a decode unit to decode a single instruction into a decoded instruction, the decoded instruction to cause the compute apparatus to perform a complex compute operation.

An apparatus to facilitate compute compression is disclosed. The apparatus includes a graphics processing unit including mapping logic to map a first block of integer pixel data to a compression block and compression logic to compress the compression block.

Targeted mapping of graphical data for compression

Growing community of inventors

Santa Clara, CA, United States of America

Nadathur Rajagopalan Satish