IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12346798 B1

PDFFull Text
Date of Patent:
Jul. 01, 2025

Filed:

Jul. 12, 2023

Dynamic precision for neural network compute operations

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Kamal Sinha, Rancho Cordova, CA (US);

Balaji Vembu, Folsom, CA (US);

Eriko Nurvitadhi, Hillsboro, OR (US);

Nicolas C. Galoppo Von Borries, Portland, OR (US);

Rajkishore Barik, Santa Clara, CA (US);

Tsung-Han Lin, Campbell, CA (US);

Joydeep Ray, Folsom, CA (US);

Ping T. Tang, Edison, NJ (US);

Michael S. Strickland, Sunnyvale, CA (US);

Xiaoming Chen, Shanghai, CN;

Anbang Yao, Beijing, CN;

Tatiana Shpeisman, Menlo Park, CA (US);

Abhishek R. Appu, El Dorado Hills, CA (US);

Altug Koker, El Dorado Hills, CA (US);

Farshad Akhbari, Chandler, AZ (US);

Narayan Srinivasa, Portland, OR (US);

Feng Chen, Shanghai, CN;

Dukhwan Kim, San Jose, CA (US);

Nadathur Rajagopalan Satish, Santa Clara, CA (US);

John C. Weast, Portland, OR (US);

Mike B. MacPherson, Portland, OR (US);

Linda L. Hurd, Cool, CA (US);

Vasanth Ranganathan, El Dorado Hills, CA (US);

Sanjeev Jahagirdar, Folsom, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:

JAFFERY WATSON HAMILTON & DESANCTIS LLP;

Primary Examiner:

Brian Ngo

Int. Cl.
CPC ...
G06N 3/00 (2023.01); G06F 1/3287 (2019.01); G06F 1/3293 (2019.01); G06F 9/30 (2018.01); G06F 15/76 (2006.01); G06F 15/78 (2006.01); G06N 3/04 (2023.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/063 (2023.01); G06N 3/08 (2023.01); G06N 3/084 (2023.01); G06T 1/20 (2006.01); G06T 15/00 (2011.01); G06T 1/60 (2006.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 1/3287 (2013.01); G06F 1/3293 (2013.01); G06F 9/30014 (2013.01); G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 15/76 (2013.01); G06F 15/78 (2013.01); G06N 3/04 (2013.01); G06N 3/044 (2023.01); G06N 3/045 (2023.01); G06N 3/08 (2013.01); G06N 3/084 (2013.01); G06T 1/20 (2013.01); G06T 15/005 (2013.01); G06T 1/60 (2013.01);
Abstract

In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

Find Patent Forward Citations

Loading…