The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 08, 2024
Filed:
Jun. 14, 2023
Intel Corporation, Santa Clara, CA (US);
Eriko Nurvitadhi, Hillsoboro, OR (US);
Balaji Vembu, Folsom, CA (US);
Nicolas C. Galoppo Von Borries, Portland, OR (US);
Rajkishore Barik, Santa Clara, CA (US);
Tsung-Han Lin, Campbell, CA (US);
Kamal Sinha, Rancho Cordova, CA (US);
Nadathur Rajagopalan Satish, Santa Clara, CA (US);
Jeremy Bottleson, Rancho Cordova, CA (US);
Farshad Akhbari, Chandler, AZ (US);
Altug Koker, El Dorado Hills, CA (US);
Narayan Srinivasa, Portland, OR (US);
Dukhwan Kim, San Jose, CA (US);
Sara S. Baghsorkhi, San Jose, CA (US);
Justin E. Gottschlich, Santa Clara, CA (US);
Feng Chen, Shanghai, CN;
Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);
Kevin Nealis, San Jose, CA (US);
Xiaoming Chen, Shanghai, CN;
Anbang Yao, Beijing, CN;
Intel Corporation, Santa Clara, CA (US);
Abstract
One embodiment provides a parallel processor comprising a hardware scheduler to schedule pipeline commands for compute operations to one or more of multiple types of compute units, a plurality of processing resources including a first sparse compute unit configured for input at a first level of sparsity and hybrid memory circuitry including a memory controller, a memory interface, and a second sparse compute unit configured for input at a second level of sparsity that is greater than the first level of sparsity.