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Santa Clara, CA, United States of America

Monir H El-Diwany

This inventor holds 12 USPTO granted patents. Top assignee: National Semiconductor Corporation. Active years: 1991-2012.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Monir H El-Diwany. Retrieved from https://idiyas.com/inventor/monir-h-el-diwany

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 12

% Patents Active = 100.0

Average Co-Inventor Count = 2.1

ph-index = 8

Forward Citations = 130(Granted Patents)


Location History:

  • Santa Clara, CA (US) (1991 - 1993)
  • Saratoga, CA (US) (1998 - 2012)

Company Filing History:

goldMedal12 out of 4,791 
 
National Semiconductor Corporation
 patents

Years Active: 1991-2012

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12 patents (USPTO):Explore Patents
1. 8148799 - Self-aligned bipolar transistor structure (2012-04-03),
2. 7687887 - Method of forming a self-aligned bipolar transistor structure using a selectively grown emitter (2010-03-30),
3. 6091111 - High voltage mos device having an extended drain region with different (2000-07-18),
4. 5953599 - Method for forming low-voltage CMOS transistors with a thin layer of (1999-09-14),
5. 5893742 - Co-implantation of arsenic and phosphorus in extended drain region for (1999-04-13),
6. 5846866 - Drain extension regions in low voltage lateral DMOS devices (1998-12-08),
7. 5766990 - Method of manufacturing a high speed bipolar transistor in a CMOS process (1998-06-16),
8. 5179031 - Method of manufacturing a polysilicon emitter and a polysilicon gate (1993-01-12),
9. 5124817 - Polysilicon emitter and a polysilicon gate using the same etch of (1992-06-23),
10. 5082796 - Use of polysilicon layer for local interconnect in a CMOS or BiCMOS (1992-01-21),
11. 5081518 - Use of a polysilicon layer for local interconnect in a CMOS or BICMOS (1992-01-14),
12. 5001081 - Method of manufacturing a polysilicon emitter and a polysilicon gate (1991-03-19),

Title: Monir H El-Diwany: Innovator in Semiconductor Technology

Introduction

Monir H El-Diwany is a prominent inventor based in Santa Clara, CA, known for his significant contributions to semiconductor technology. With a total of 12 patents to his name, he has made remarkable advancements in the field of bipolar transistors.

Latest Patents

Among his latest patents is a self-aligned bipolar transistor structure. This innovative design features a semiconductor substrate with a first conductivity type and a collector region with a second conductivity type, which is opposite to the first. The structure is defined by isolation dielectric material on the upper surface of the semiconductor substrate. Additionally, the base region includes an intrinsic base region and an extrinsic base region, along with a sloped in-situ doped emitter plug. Another notable patent involves a method for forming a self-aligned bipolar transistor structure using a selectively grown emitter. This method utilizes the selective growth of a doped silicon emitter in a sloped oxide emitter window, enhancing the self-aligned structure's efficiency.

Career Highlights

Monir H El-Diwany has had a distinguished career at National Semiconductor Corporation, where he has played a crucial role in developing advanced semiconductor technologies. His work has significantly impacted the industry, leading to innovations that improve the performance and reliability of electronic devices.

Collaborations

Throughout his career, Monir has collaborated with esteemed colleagues, including Michael P Brassington and Reda R Razouk. These partnerships have fostered a creative environment that has led to groundbreaking advancements in semiconductor technology.

Conclusion

Monir H El-Diwany's contributions to the field of semiconductor technology are noteworthy, with his innovative patents and collaborations paving the way for future advancements. His work continues to influence the industry and inspire new generations of inventors.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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