National Semiconductor Corporation

Monir H El-Diwany

Reda R Razouk

Michael P Brassington

Prateep Tuntasood

Alexei Sadovnikov

Jamal Ramdani

Esin Kutlu Demirlioglu

Robert Ys Huang

A bipolar transistor structure comprises a semiconductor substrate having a first conductivity type, a collector region having a second conductivity type that is opposite the first conductivity type formed in a substrate active device region defined by isolation dielectric material formed in an upper surface of the semiconductor substrate, a base region that includes an intrinsic base region having the first conductivity type formed over the collector region and an extrinsic base region having the second conductivity type formed over the isolation dielectric material, and a sloped in-situ doped emitter plug having the second conductivity type formed on the intrinsic base region.

Self-aligned bipolar transistor structure

A method for forming a self-aligned bipolar transistor structure uses the selective growth of a doped silicon emitter in a sloped oxide emitter window to form the self-aligned structure. In an alternate process flow, the top emitter layer is SiGe with a high Ge content that is etched off selectively after deposition of the extrinsic base layer. In another alternate flow, a nitride plug formed on top of the emitter blocks the extrinsic base implant from the emitter region.

Method of forming a self-aligned bipolar transistor structure using a selectively grown emitter

A high voltage MOS device includes a P-type substrate having an N-type buried layer formed therein. An N-type epitaxial layer overlies the substrate and a P-type well is formed in the epitaxial layer. A source region is formed in the well such that the source region is directly in contact with the well. No intermediate layer is disposed between the source region and the well. A drain region includes an extended drain region. The extended drain region, which is formed within and in contact with the well, comprises different dopant species and has a maximum dopant concentration of 3.5.times.10.sup.17 cm.sup.-3. A heavily doped main drain region is formed within and in contact with the extended drain region. The source region and extended drain region define a channel region therebetween in the well. An insulator is on a surface of the well over the channel region. A gate is over the insulator.

High voltage mos device having an extended drain region with different

The low-voltage, e.g., 2.5-volt, transistors that support the logic operations of a CMOS device are formed to have a thin layer of gate oxide, while the high-voltage, e.g., 3.3 or 5-volt, transistors that support the analog operations of the device are formed to have a thick layer of gate oxide in a cost-effective process flow that requires only one additional masking step over a conventional double-poly CMOS process.

Method for forming low-voltage CMOS transistors with a thin layer of

A high voltage NMOS device includes an extended drain region formed by implantation of arsenic and phosphorus and a drivein of both the species. The dosage of arsenic is substantially higher than the dosage of phosphorus, so that upon drivein, the slower diffusing arsenic is highly concentrated near the surface of the extended drain region, while the more rapidly diffusing phosphorus provides a gradual gradient of concentration of dopant into the extended drain region.

Co-implantation of arsenic and phosphorus in extended drain region for

Disclosed are MOSFET devices in which a region extends from the drain and is, self-aligned with the gate. The region has a lower dopant concentration than the drain. The presence of the extension region substantially enhances breakdown voltage while not adding excessive on-resistance for the devices.

Drain extension regions in low voltage lateral DMOS devices

Fabrication of a high frequency bipolar transistor structure is integrated into a CMOS process flow with minimal additional cost. The polysilicon emitter of the bipolar device and the polysilicon gate of the MOS device use separate polysilicon layers and, therefore, allow the bipolar emitter and the MOS gate to be doped independently of each other. The process scheme does not require the MOS device to be subdivided.

Method of manufacturing a high speed bipolar transistor in a CMOS process

A method of making bipolar and MOS devices simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for forming the emitter and gates of the bipolar and MOS devices, respectively.

Method of manufacturing a polysilicon emitter and a polysilicon gate

Bipolar and MOS devices are made simultaneously using a single fabrication process. In one embodiment of the invention, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide, having a thickness in the range of from approximately 150 angstroms to 300 angstroms, is thermally grown on the silicon substrate. A thin layer of polycrystalline silicon, having a thickness in the range of from approximately 500 angstroms to 1000 angstroms is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing. Both the thin polysilicon layer and the gate oxide layer are removed from the bipolar region where the emitter is to be formed. To maintain the integrity of the gate oxide layer during etching, a photoresist mask used during the polysilicon etch is retained during the gate oxide etch, and the gate oxide is etched in a buffered oxide solution. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for forming the emitter and gates of the bipolar and MOS devices, respectively.

Polysilicon emitter and a polysilicon gate using the same etch of

A method of constructing a semiconductor structure wherein the polysilicon gate layer in a CMOS or BiCMOS structure incorporating LDD structures may be used for local interconnect. In one embodiment of the invention directed to a BiCMOS process, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide then is thermally grown on the silicon substrate. A thin layer of polysilicon is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing, and then both the thin polysilicon layer and the gate oxide layer are etched from the bipolar and MOS regions where the respective emitter and gates are to be formed and where buried contacts are to be made. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for defining the bipolar emitter, the MOS gates, and the local interconnects. A conformal silicon dioxide layer is subsequently deposited and etched for forming oxide spacers on the sidewalls of the polysilicon layer. By selectively doping the polysilicon layer and exposed portions of the substrate, a continuous active region is formed beneath the polysilicon layer and the sidewall spacers.

Use of polysilicon layer for local interconnect in a CMOS or BiCMOS

A method of constructing a semiconductor structure wherein the polysilicon gate layer in a CMOS or BICMOS structure incorporating LDD structures may be used for local interconnect. In one embodiment of the invention directed to a BiCMOS process, a silicon substrate is divided into bipolar and MOS regions. A thin layer of gate oxide then is thermally grown on the silicon substrate. A thin layer of polysilicon is deposited on the gate oxide layer to protect the gate oxide layer during subsequent processing, and then both the thin polysilicon layer and the gate oxide layer are etched from the bipolar and MOS regions where the respective emitter and gates are to be formed and where buried contacts are to be made. A thick layer of polysilicon then is deposited on the bipolar and MOS regions of the silicon substrate, and the substrate is masked and etched for defining the bipolar emitter, the MOS gates, and the local interconencts. A conformal silicon dioxide layer is subsequently deposited and etched for forming oxide spacers on the sidewalls of the polysilicon layer. By selectively doping the polysilicon layer and exposed portions of the substrate, a continuous active region is formed beneath the polysilicon layer and the sidewall spacers.

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Santa Clara, CA, United States of America

Monir H El-Diwany