Mohamad A Shaheen

This inventor holds 26 USPTO granted patents and 3 published patent applications, primarily in Semiconductor Technology. Top assignees: Intel Corporation, Soitec. Active years: 2003-2014.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Mohamad A Shaheen. Retrieved from https://idiyas.com/inventor/mohamad-a-shaheen

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 26 (Patent Applications = 3)

% Patents Active = 3.8

Average Co-Inventor Count = 3.1

ph-index = 8

Forward Citations = 493(Granted Patents)

Company Filing History:

Years Active: 2003-2014

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Areas of Expertise:

III-V Integration

Strained Structures

Buffer Architectures

Silicon Substrates

High Mobility Devices

Quantum Well Structures

Epitaxial Bonding

Silicon-On-Insulator

Thermal Management

Device Isolation

Laser-Induced Cleaving

Dual Orientation Bonding

26 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 8735946 - Substrate having a charged zone in an insulating buried layer (2014-05-27),

2. 8617945 - Stacking fault and twin blocking barrier for integrating III-V on Si (2013-12-31),

3. 8535996 - Substrate having a charged zone in an insulating buried layer (2013-09-17),

4. 8143646 - Stacking fault and twin blocking barrier for integrating III-V on Si (2012-03-27),

5. 8084818 - High mobility tri-gate devices and methods of fabrication (2011-12-27),

6. 8034675 - Semiconductor buffer architecture for III-V devices on silicon substrates (2011-10-11),

7. 7851781 - Buffer layers for device isolation of devices grown on silicon (2010-12-14),

8. 7851780 - Semiconductor buffer architecture for III-V devices on silicon substrates (2010-12-14),

9. 7723749 - Strained semiconductor structures (2010-05-25),

10. 7670928 - Ultra-thin oxide bonding for S1 to S1 dual orientation bonding (2010-03-02),

11. 7573059 - Dislocation-free InSb quantum well structure on Si using novel buffer architecture (2009-08-11),

12. 7494911 - Buffer layers for device isolation of devices grown on silicon (2009-02-24),

13. 7473614 - Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer (2009-01-06),

14. 7378331 - Methods of vertically stacking wafers using porous silicon (2008-05-27),

15. 7355247 - Silicon on diamond-like carbon devices (2008-04-08),

Title: Innovations and Contributions of Mohamad A. Shaheen

Introduction

Mohamad A. Shaheen is a prominent inventor based in Portland, OR, whose innovative work has led to the development of 26 patents. His contributions span various fields, particularly in semiconductor technology, where he has explored advanced materials and processes that enhance device performance.

Latest Patents

Among his most recent patents is the invention of a substrate featuring a charged zone in an insulating buried layer. This innovation describes substrates made up of a base wafer, an insulating layer, and a top semiconductor layer, with the insulating layer containing a charged zone that significantly enhances its properties. Moreover, he has developed a method for a stacking fault and twin blocking barrier that facilitates the integration of III-V devices on silicon substrates. This invention allows for the formation of III-V InSb device layers on silicon while maintaining low defect densities, achieved through the strategic placement of a buffer layer.

Career Highlights

Mohamad A. Shaheen has built an impressive career, working with notable companies such as Intel Corporation and Soitec. His experience in these leading organizations has equipped him with a wealth of knowledge and expertise in semiconductor device manufacturing and innovation.

Collaborations

Throughout his career, Shaheen has collaborated with distinguished professionals in the field, including Peter G. Tolchinsky and Mantu K. Hudait. These collaborations have contributed to his successful patents and advancements in device technology.

Conclusion

In summary, Mohamad A. Shaheen's extensive portfolio of patents and his work with influential companies underscore his impactful contributions to the field of semiconductor technology. His innovations pave the way for future advancements and inspire ongoing research and development in the industry.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

3 patents pending: