The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2009
Filed:
Sep. 27, 2006
Mantu K. Hudait, Portland, OR (US);
Mohamad A. Shaheen, Portland, OR (US);
Loren A. Chow, Santa Clara, CA (US);
Peter G. Tolchinsky, Beaverton, OR (US);
Joel M. Fastenau, Bethlehem, PA (US);
Dmitri Loubychev, Bethlehem, PA (US);
Amy W. K. Liu, Mountain View, CA (US);
Mantu K. Hudait, Portland, OR (US);
Mohamad A. Shaheen, Portland, OR (US);
Loren A. Chow, Santa Clara, CA (US);
Peter G. Tolchinsky, Beaverton, OR (US);
Joel M. Fastenau, Bethlehem, PA (US);
Dmitri Loubychev, Bethlehem, PA (US);
Amy W. K. Liu, Mountain View, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Various embodiments proved a buffer layer that is grown over a silicon substrate that provides desirable isolation for devices formed relative to III-V material device layers, such as InSb-based devices, as well as bulk thin film grown on a silicon substrate. In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate. In addition, the buffer layer addresses and mitigates lattice mismatches between the film relative to which the transistor is formed and the silicon substrate.