The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 14, 2010
Filed:
Aug. 02, 2006
Mantu K. Hudait, Portland, OR (US);
Mohamad A. Shaheen, Portland, OR (US);
Dmitri Loubychev, Behtlethem, PA (US);
Amy W. K. Liu, Mountain View, CA (US);
Joel M. Fastenau, Bethlehem, PA (US);
Mantu K. Hudait, Portland, OR (US);
Mohamad A. Shaheen, Portland, OR (US);
Dmitri Loubychev, Behtlethem, PA (US);
Amy W. K. Liu, Mountain View, CA (US);
Joel M. Fastenau, Bethlehem, PA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A composite buffer architecture for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×10cmto be formed on silicon substrates. In an embodiment of the present invention, a dual buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations and provide electrical isolation. In an embodiment of the present invention, the material of each buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a GaSb/AlSb buffer is utilized to form an InSb-based quantum well transistor on a silicon substrate.