The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 11, 2009
Filed:
Aug. 02, 2006
Mantu K. Hudait, Portland, OR (US);
Mohamad A. Shaheen, Portland, OR (US);
Loren A. Chow, Santa Clara, CA (US);
Peter G. Tolchinsky, Beaverton, OR (US);
Dmitri Loubychev, Bethlehem, PA (US);
Joel M. Fastenau, Bethlehem, PA (US);
Amy W. K. Liu, Mountain View, CA (US);
Mantu K. Hudait, Portland, OR (US);
Mohamad A. Shaheen, Portland, OR (US);
Loren A. Chow, Santa Clara, CA (US);
Peter G. Tolchinsky, Beaverton, OR (US);
Dmitri Loubychev, Bethlehem, PA (US);
Joel M. Fastenau, Bethlehem, PA (US);
Amy W. K. Liu, Mountain View, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A device grade III-V quantum well structure formed on a silicon substrate using a composite buffer architecture and the method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×10cmto be formed on silicon substrates. In an embodiment of the present invention, an InSb quantum well layer is sandwiched between two larger band gap barrier layers. In an embodiment of the present invention, InSb quantum well layer is strained. In a specific embodiment, the two larger band gap barrier layers are graded.