The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 27, 2008
Filed:
Dec. 29, 2004
Mohamad Shaheen, Portland, OR (US);
Peter G. Tolchinsky, Beaverton, OR (US);
Irwin Yablok, Portland, OR (US);
Scott R. List, Overijse, BE;
Mohamad Shaheen, Portland, OR (US);
Peter G. Tolchinsky, Beaverton, OR (US);
Irwin Yablok, Portland, OR (US);
Scott R. List, Overijse, BE;
Intel Corporation, Santa Clara, CA (US);
Abstract
A method and article to provide a three-dimensional (3-D) IC wafer process flow. In some embodiments, the method and article include bonding a device layer of a multilayer wafer to a device layer of another multilayer wafer to form a bonded pair of device layers, each of the multilayer wafers including a layer of silicon on a layer of porous silicon (SiOPSi) on a silicon substrate where the device layer is formed in the silicon layer, separating the bonded pair of device layers from one of the silicon substrates by splitting one of the porous silicon layers, and separating the bonded pair of device layers from the remaining silicon substrate by splitting the other one of the porous silicon layers to provide a vertically stacked wafer.