Kaohsiung, Taiwan

Min-Yann Hsieh

This inventor holds 25 USPTO granted patents and 4 published patent applications, primarily in Semiconductor Fabrication. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., Parabellum Strategic Opportunties Fund LLC. Active years: 2018-2025.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Min-Yann Hsieh. Retrieved from https://idiyas.com/inventor/min-yann-hsieh

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 25 

% Patents Active = 100.0

Average Co-Inventor Count = 4.3

ph-index = 4

Forward Citations = 56(Granted Patents)


Location History:

  • Hsin-Chu, TW (2018 - 2020)
  • Kaohsiung, TW (2018 - 2024)

Company Filing History:


Years Active: 2018-2025

Loading Chart...
Areas of Expertise:
Contact Plugs
Dielectric Fins
Cobalt-Based Interconnects
Semiconductor Device
FinFET Structure
Integrated Circuit Patterning
Self-Aligned Contacts
Embedded Memory Device
25 patents (USPTO):Explore Patents

Title: **Min-Yann Hsieh: Innovating Semiconductor Technology in Kaohsiung**

Introduction

Min-Yann Hsieh is a prominent inventor based in Kaohsiung, Taiwan. With an impressive portfolio of 21 patents, he significantly contributes to the field of semiconductor technology. His innovative work focuses primarily on interconnect structures and methods of fabrication, showcasing his expertise and commitment to advancing the industry.

Latest Patents

Among his latest patents, one notable innovation is titled “Vias for cobalt-based interconnects and methods of fabrication thereof.” This patent outlines interconnect structures and corresponding techniques for forming them. The exemplary interconnect structure features a conductive element that includes cobalt, with a via positioned over it. The via is intricately designed, comprising a first barrier layer of titanium, a second barrier layer of titanium and nitrogen, and a bulk layer made of tungsten and/or cobalt. Additionally, a capping layer may be included to enhance the functionality of the structure.

Another important patent emphasizes “Contact plugs and methods forming same.” This methodology describes a comprehensive process for forming a transistor, beginning with a dummy gate stack over a semiconductor region. The development involves several advanced layers, including an Inter-Layer Dielectric (ILD) and a low-k gate spacer. The techniques outlined ensure effective formation and planarization of the metal gate and dielectric, contributing to more efficient semiconductor devices.

Career Highlights

Min-Yann Hsieh currently works at Taiwan Semiconductor Manufacturing Company Limited, a key player in the semiconductor industry. His work at the company has cemented his status as a key contributor to cutting-edge semiconductor research. Hsieh's numerous patents reflect his ability to innovate and adapt to the ever-evolving technological landscape.

Collaborations

Throughout his career, Min-Yann Hsieh has collaborated with notable colleagues, including Kuo-Hua Pan and Hua Feng Chen. These partnerships have fostered a collaborative environment that drives forward-thinking solutions in semiconductor technology, enhancing both individual and collective achievements.

Conclusion

Min-Yann Hsieh’s innovative contributions to the field of semiconductor technology through his numerous patents illustrate his role as a leader in the industry. As he continues to work at Taiwan Semiconductor Manufacturing Company Limited, his efforts will likely influence the future of semiconductor design and fabrication, cementing his legacy as an influential inventor in Kaohsiung and beyond.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
Loading…