Masatomo Hasegawa

This inventor holds 16 USPTO granted patents. Top assignees: Fujitsu Corporation, Fujitsu Microelectronics Limited. Active years: 1997-2010.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Masatomo Hasegawa. Retrieved from https://idiyas.com/inventor/masatomo-hasegawa

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 16

% Patents Active = 87.5

Average Co-Inventor Count = 5.9

ph-index = 8

Forward Citations = 261(Granted Patents)

Company Filing History:

Fujitsu Microelectronics Limited

patents

Years Active: 1997-2010

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16 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 7706209 - Semiconductor memory device capable of driving non-selected word lines to a variable negative potential based on a bank access operation (2010-04-27),

2. 7079443 - Semiconductor device (2006-07-18),

3. 6628564 - Semiconductor memory device capable of driving non-selected word lines to first and second potentials (2003-09-30),

4. 6618320 - Semiconductor memory device (2003-09-09),

5. 6605963 - Semiconductor integrated circuit and method of switching source potential of transistor in semiconductor integrated circuit (2003-08-12),

6. 6252269 - Semiconductor memory device (2001-06-26),

7. 6246628 - Semiconductor memory device having read/write amplifiers disposed for respective memory segments (2001-06-12),

8. 6229363 - Semiconductor device (2001-05-08),

9. 6201378 - Semiconductor integrated circuit (2001-03-13),

10. 6198686 - Memory device having row decoder (2001-03-06),

11. 6172537 - Semiconductor device (2001-01-09),

12. 6147919 - Semiconductor memory employing direct-type sense amplifiers capable of (2000-11-14),

13. 6115284 - Memory device with faster write operation (2000-09-05),

14. 6111795 - Memory device having row decoder (2000-08-29),

15. 6072749 - Memory device preventing a slow operation through a mask signal (2000-06-06),

Title: Masatomo Hasegawa: Innovator in Semiconductor Technology

Introduction

Masatomo Hasegawa is a prominent inventor based in Kawasaki, Japan. He has made significant contributions to the field of semiconductor technology, holding a total of 16 patents. His work focuses on enhancing the performance and efficiency of semiconductor devices.

Latest Patents

Hasegawa's latest patents include a semiconductor memory device capable of driving non-selected word lines to a variable negative potential based on a bank access operation. This innovative semiconductor device features a word line driver that resets the word line connected to a memory cell in a memory cell array. The reset level of the word line driver can be switched between first and second potentials, allowing for improved functionality. Additionally, his patents describe a word line reset level generating circuit that varies the amount of negative potential current supply according to the operating conditions of the memory cell array. This advancement enables the semiconductor device to optimize performance by adjusting the current supply of the word line reset level generating circuit.

Career Highlights

Throughout his career, Masatomo Hasegawa has worked with notable companies such as Fujitsu Corporation and Fujitsu Microelectronics Limited. His experience in these organizations has allowed him to develop cutting-edge technologies in the semiconductor industry.

Collaborations

Hasegawa has collaborated with talented individuals in his field, including Masato Matsumiya and Masato Takita. These partnerships have contributed to the advancement of semiconductor technology and innovation.

Conclusion

Masatomo Hasegawa's contributions to semiconductor technology through his patents and collaborations highlight his role as a leading inventor in the industry. His work continues to influence the development of efficient and advanced semiconductor devices.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]