The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2003

Filed:

Oct. 05, 1999
Applicant:
Inventors:

Ayako Kitamoto, Kawasaki, JP;

Masato Matsumiya, Kawasaki, JP;

Satoshi Eto, Kawasaki, JP;

Masato Takita, Kawasaki, JP;

Toshikazu Nakamura, Kawasaki, JP;

Hideki Kanou, Kawasaki, JP;

Kuninori Kawabata, Kawasaki, JP;

Masatomo Hasegawa, Kawasaki, JP;

Toru Koga, Kawasaki, JP;

Yuki Ishii, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 1/9185 ;
U.S. Cl.
CPC ...
H03K 1/9185 ;
Abstract

A semiconductor integrated circuit, comprising a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit by a combination of a plurality of transistors, is disclosed. Among a plurality of the transistors of the circuit unit, the source potential of at least one transistor adapted to turn off during the standby period of the circuit unit is changed. Preferably, the semiconductor integrated circuit is configured to reduce the sub-threshold current flowing between the source and the drain of at least one transistor adapted to turn off during the standby period of the circuit unit by changing the source potential at a timing based on the standby period of the circuit unit in such a manner that a predetermined bias voltage is applied between the gate and the source of the transistor. A method of switching the source potential of at least one transistor in the semiconductor integrated circuit having the configuration described above is also disclosed.


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