The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2001

Filed:

Jul. 10, 2000
Applicant:
Inventors:

Masato Takita, Kawasaki, JP;

Masato Matsumiya, Kawasaki, JP;

Masatomo Hasegawa, Kawasaki, JP;

Toshimi Ikeda, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 8/00 ;
U.S. Cl.
CPC ...
G11C 8/00 ;
Abstract

On one hand, a row address is provided via a buffer gate to a row address register,, and its output is provided via a complementary signal generation circuit,and a predecoder,to a word decoder,A. On the other hand, in response to an issuance of-an activate command a control signal AS,is provided via a delay circuit,to the clock input CK of the row address register,as a strobe signal AS,, and AS,is provided, to reduce timing margin, via a delay circuit,A to the strobe signal input of the predecoder,as a strobe signal S,. S,is provided via a delay circuit,B to the strobe signal input of the word decoder,A having RS flip-flops,to,or latch circuits. Each of the latch circuits consists of a NOR gate having a set input and a reset input and another NOR gate having an input coupled to receive the output of the former NOR gate and another set input to receive a multiple selection signal which is common for all the latch circuits in word decoders.


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