The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 26, 2001
Filed:
Oct. 25, 1999
Masatomo Hasegawa, Kawasaki, JP;
Masato Matsumiya, Kawasaki, JP;
Satoshi Eto, Kawasaki, JP;
Masato Takita, Kawasaki, JP;
Toshikazu Nakamura, Kawasaki, JP;
Ayako Kitamoto, Kawasaki, JP;
Kuninori Kawabata, Kawasaki, JP;
Hideki Kanou, Kawasaki, JP;
Toru Koga, Kawasaki, JP;
Yuki Ishii, Kawasaki, JP;
Fujitsu Limited, Kanagawa, JP;
Abstract
According to a semiconductor memory for one aspect of the present invention, a memory cell transistor is formed in a P-type first well region which is formed at the surface of a P-type semiconductor substrate, and a back bias voltage is applied to the P-type first well region and the P-type substrate. Further, an N-type retrograde region is formed by implanting a high energy N-type impurity, so that a deeper, N-type second well region is formed by employing the N-type retrograde region. Further, a P-type third well region is formed in the N-type second well region, and a P-type emitter region is also formed therein. Thus, together the P-type emitter region, the N-type second well region, and the P-type third well region constitute a lateral PNP transistor. In addition, the ground voltage is maintained for the P-type third well region, which serves as a collector region.