The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2006

Filed:

Aug. 01, 2003
Applicants:

Masato Takita, Kawasaki, JP;

Masato Matsumiya, Kawasaki, JP;

Satoshi Eto, Kawasaki, JP;

Toshikazu Nakamura, Kawasaki, JP;

Masatomo Hasegawa, Kawasaki, JP;

Ayako Kitamoto, Kawasaki, JP;

Kuninori Kawabata, Kawasaki, JP;

Hideki Kanou, Kawasaki, JP;

Toru Koga, Kawasaki, JP;

Yuki Ishii, Kawasaki, JP;

Shinichi Yamada, Kawasaki, JP;

Kaoru Mori, Kawasaki, JP;

Inventors:

Masato Takita, Kawasaki, JP;

Masato Matsumiya, Kawasaki, JP;

Satoshi Eto, Kawasaki, JP;

Toshikazu Nakamura, Kawasaki, JP;

Masatomo Hasegawa, Kawasaki, JP;

Ayako Kitamoto, Kawasaki, JP;

Kuninori Kawabata, Kawasaki, JP;

Hideki Kanou, Kawasaki, JP;

Toru Koga, Kawasaki, JP;

Yuki Ishii, Kawasaki, JP;

Shinichi Yamada, Kawasaki, JP;

Kaoru Mori, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/08 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array. Furthermore, in a semiconductor device including a plurality of power source circuits each having an oscillation circuit and a capacitor, for driving the capacitor by the oscillation signal outputted by the oscillation circuit, at least a part of these power source circuits shares in common the oscillation circuit, and different capacitors are driven by the oscillation signal outputted from the common oscillation circuit.


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