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For the Inventor, By the Inventor

Plano, TX, United States of America

Manoj K Jain

USPTO Granted Patents = 32 

Average Co-Inventor Count = 1.6

ph-index = 11

Forward Citations = 439(Granted Patents)


Location History:

  • Silver Spring, MD (US) (2003)
  • Plano, TX (US) (1996 - 2024)

Company Filing History:

goldMedal30 out of 29,232 
 
Texas Instruments Corporation
 patents
silverMedal1 out of 1 
 
Taxas Instruments Incorporated
 patent
bronzeMedal1 out of 832,680 
Other
 patents

Years Active: 1996-2025

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32 patents (USPTO):Explore Patents
1. 12261141 - IC device with chip to package interconnects from a copper metal interconnect level (2025-03-25),
2. 12125811 - Semiconductor structure and method for wafer scale chip package (2024-10-22),
3. 12080755 - Multi-layer polysilicon stack for semiconductor devices (2024-09-03),
4. 11888021 - Reduced ESR in trench capacitor (2024-01-30),
5. 11456267 - Fet construction with copper pillars or bump directly over the fet (2022-09-27),
6. 11271072 - Trench capacitor with warpage reduction (2022-03-08),
7. 10811312 - Method of using a sacrificial conductive stack to prevent corrosion (2020-10-20),
8. 10720490 - Integrated trench capacitor formed in an epitaxial layer (2020-07-21),
9. 10586844 - Integrated trench capacitor formed in an epitaxial layer (2020-03-10),
10. 10559650 - Trench capacitor with warpage reduction (2020-02-11),
11. 10490448 - Method of using a sacrificial conductive stack to prevent corrosion (2019-11-26),
12. 9865555 - Self-aligned under bump metal (2018-01-09),
13. 9627334 - Self-aligned under bump metal (2017-04-18),
14. 9607926 - Probe pad design to reduce saw defects (2017-03-28),
15. 9478510 - Self-aligned under bump metal (2016-10-25),

Title: Innovations by Manoj K Jain: A Leader in Semiconductor Technologies

Introduction

Manoj K Jain, based in Plano, TX, is an accomplished inventor with a remarkable portfolio of 30 patents. His work primarily focuses on advancements in semiconductor technologies, reflecting a commitment to innovation and excellence in the field.

Latest Patents

Among his most recent contributions are two notable patents. The first is a semiconductor structure and method for wafer scale chip packages. This innovation includes a metal layer, a redistribution layer (RDL) structure featuring an RDL platform, and multiple RDL pillars that form electrical connections via an under-bump metal (UBM) layer and a solder bump. These features enhance the efficiency and functionality of semiconductor packaging.

The second patent details a multi-layer polysilicon stack for semiconductor devices. This method for forming a capacitor comprises creating a doped polysilicon layer over a semiconductor substrate, followed by the application of a dielectric layer and an undoped polysilicon layer. This innovative approach enhances capacitor design and functionality within semiconductor devices.

Career Highlights

Throughout his career, Manoj K Jain has made significant contributions while working with prestigious companies, including Texas Instruments Corporation. His experience has enabled him to pioneer various technologies that have a lasting impact on the semiconductor industry.

Collaborations

Manoj has collaborated with several talented individuals, including coworkers Yunlong Liu and He Lin. These collaborations have enriched his work, fostering innovation and the exchange of ideas that propel advancements in semiconductor technologies.

Conclusion

Manoj K Jain stands out as a prominent figure in the realm of semiconductor innovations. His extensive patent portfolio and collaborative efforts underscore his dedication to advancing technology and engineering solutions that address critical industry challenges. With a strong foundation in research and development, Jain continues to inspire the next generation of inventors in the semiconductor field.

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