The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 25, 2025
Filed:
May. 27, 2021
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventor:
Manoj Kumar Jain, Plano, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 24/20 (2013.01); H01L 21/565 (2013.01); H01L 21/76877 (2013.01); H01L 23/53228 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 24/19 (2013.01); H01L 24/82 (2013.01); H01L 24/94 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13655 (2013.01); H01L 2224/13664 (2013.01); H01L 2224/14505 (2013.01); H01L 2224/2101 (2013.01); H01L 2224/215 (2013.01);
Abstract
An integrated circuit device () and method comprising an IC chip () having metal interconnect levels (M-Mn) including a last copper interconnect level (Mn) and a chip-to-package interconnect () overlying and connected to the last copper interconnect level (Mn). The chip-to-package interconnect () having a via () connected to a first element () of the last copper interconnect level (Mn) and a copper conductive structure () (e.g., bump copper). The via () includes a barrier material () and a tungsten fill layer (), the via coupled between the copper conductive structure () and the first element ().