Texas Instruments Corporation

Other

Taxas Instruments Incorporated

Manoj K Jain

Yunlong Liu

He Lin

Jiao Jia

Scott Robert Summerfelt

Kezhakkedath Ramunni Udayakumar

Michael F Chisholm

Ted S Moise

Robert H Havemann

Zhipeng Feng

Zhi Peng Feng

Sreenivasan Kalyani Koduri

Bhaskar Srinivasan

Haowen Bu

Jeffrey Alan West

Girish Anant Dixit

Indumini W Ranmuthu

Qi-Zhong Hong

Brian Goodlin

Rui Liu

Eden M Zielinski

Furen Lin

Eric H Warninghoff

Alan G Merriam

Chao Zuo

Shengpin Yang

Tracy S Paulsen

Jing Hu

Rui Song

Dongsheng Liu

An integrated circuit device () and method comprising an IC chip () having metal interconnect levels (M-Mn) including a last copper interconnect level (Mn) and a chip-to-package interconnect () overlying and connected to the last copper interconnect level (Mn). The chip-to-package interconnect () having a via () connected to a first element () of the last copper interconnect level (Mn) and a copper conductive structure () (e.g., bump copper). The via () includes a barrier material () and a tungsten fill layer (), the via coupled between the copper conductive structure () and the first element ().

IC device with chip to package interconnects from a copper metal interconnect level

An embodiment semiconductor structure includes a metal layer. The semiconductor structure also includes a redistribution layer (RDL) structure including an RDL platform and a plurality of RDL pillars disposed between the RDL platform and the metal layer. Additionally, the semiconductor structure includes an under-bump metal (UBM) layer disposed on the RDL platform and a solder bump disposed on the UBM layer, where the UBM layer, the RDL platform, and the RDL pillars form an electrical connection between the solder bump and the metal layer.

Semiconductor structure and method for wafer scale chip package

In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.

Multi-layer polysilicon stack for semiconductor devices

A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

Reduced ESR in trench capacitor

A method of forming a semiconductor device with a metal pillar overlapping a first top metal interconnect and a second top metal interconnect is disclosed. The metal pillar overlapping the first top metal interconnect and second top metal interconnect is connected to the first top metal interconnect by top metal vias while the second top metal interconnect does not contain top metal vias and remains free of a direct electrical connection to the metal pillar. The metal pillars are attached directly to top metal vias without a bond pad of metal. The elimination of the bond pad layer reduces the mask count, processing, and cost of the device. In addition, the elimination of the bond pad results in reduced die area requirements for the metal pillar.

Fet construction with copper pillars or bump directly over the fet

A trench capacitor includes a plurality of trenches in a semiconductor substrate. A first polysilicon layer is located within the plurality of trenches and over a top surface of the substrate. The first polysilicon layer is continuous between the plurality of trenches. The trench capacitor further includes a plurality of second polysilicon layers. Each of the second polysilicon layers fills a corresponding trench of the plurality of trenches. The second polysilicon layers each extend to a top surface of the first polysilicon layer.

Trench capacitor with warpage reduction

A method of fabricating an integrated circuit (IC) chip is disclosed. The method starts with opening a window on a first surface of the IC chip through a passivation overcoat to expose the copper metallization layer. The window has sidewalls and a bottom that is adjacent the copper metallization layer. The method continues with depositing a barrier conductive stack on the passivation overcoat and exposed portions of the copper metallization layer, then depositing a sacrificial conductive stack on the barrier conductive stack. The sacrificial conductive stack has a thickness between 50 &#x212b; and 500 &#x212b;. The first surface of the semiconductor chip is polished to remove the sacrificial conductive stack and the barrier conductive stack from the surface of the passivation overcoat.

Method of using a sacrificial conductive stack to prevent corrosion

A trench capacitor includes at least one epitaxial semiconductor surface layer on a semiconductor substrate having a doping level that is less than a doping level of the semiconductor substrate. A plurality of trenches are formed through at least one half of a thickness of the epitaxial semiconductor surface layer. The epitaxial semiconductor surface layer is thicker than a depth of the plurality of trenches. At least one capacitor dielectric layer lines a surface of the trenches. At least one trench fill layer on the dielectric layer fills the trenches.

Integrated trench capacitor formed in an epitaxial layer

A trench capacitor includes a plurality of trenches in a doped semiconductor surface layer of a substrate. At least one dielectric layer lines a surface of the plurality of trenches. A second polysilicon layer that is doped is on a first polysilicon layer that is on the dielectric layer which fills the plurality of trenches. The second polysilicon layer has a higher doping level as compared to the first polysilicon layer.

An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

Self-aligned under bump metal

An integrated circuit wafer and fabrication method includes a probe pad structure in saw lanes between integrated circuits. The probe pad structure includes a probe pad with a plurality of pad segments. The pad segments are elements of an interconnect level of the wafer.

Growing community of inventors

Plano, TX, United States of America

Manoj K Jain