The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2024

Filed:

Sep. 29, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Jing Hu, Chengdu, CN;

Zhi Peng Feng, Chengdu, CN;

Chao Zuo, Chengdu, CN;

Dongsheng Liu, Chengdu, CN;

Yunlong Liu, Chengdu, CN;

Manoj K Jain, Plano, TX (US);

Shengpin Yang, Chengdu, CN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/762 (2006.01); H01L 49/02 (2006.01); H01L 21/324 (2006.01); H01L 21/225 (2006.01); H01L 21/74 (2006.01); H01L 29/94 (2006.01); H01L 21/3215 (2006.01);
U.S. Cl.
CPC ...
H01L 28/87 (2013.01); H01L 21/2253 (2013.01); H01L 21/324 (2013.01); H01L 21/32155 (2013.01); H01L 21/743 (2013.01); H01L 21/76237 (2013.01); H01L 28/40 (2013.01); H01L 29/945 (2013.01);
Abstract

A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.


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