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For the Inventor, By the Inventor

Hsinchu, Taiwan

Li-Feng Teng

This inventor holds 36 USPTO granted patents and 16 published patent applications, primarily in Semiconductor Manufacturing. Top assignees: Taiwan Semiconductor Manufacturing Comp. Ltd., National Yang Ming Chiao Tung University, Au Optronics Corporation. Active years: 2013-2026.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Li-Feng Teng. Retrieved from https://idiyas.com/inventor/li-feng-teng

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

USPTO Granted Patents = 36 

% Patents Active = 88.9

Average Co-Inventor Count = 2.8

ph-index = 4

Forward Citations = 48(Granted Patents)


Location History:

  • Taoyuan County, TW (2013 - 2015)
  • Hsinchu, TW (2013 - 2024)

Company Filing History:

goldMedal31 out of 42,872 
 
Taiwan Semiconductor Manufacturing Comp. Ltd.
 patents
silverMedal4 out of 1,247 
 
National Yang Ming Chiao Tung University
 patents
bronzeMedal1 out of 4,577 
 
Au Optronics Corporation
 patents

Years Active: 2013-2026

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Areas of Expertise:
Semiconductor Device
FinFET
E-Fuse
Embedded Memory
High Voltage Devices
Thin Film Transistor
Integrated Circuit
Array Boundary Structure
Non-Volatile Memory
Gate Electrode
HKMG
Mask Design
36 patents (USPTO):Explore Patents
1. 12648436 - Semiconductor device having an inductor disposed within a first bonding layer and a second bonding layer (2026-06-02),
2. 12507471 - Semiconductor device and method for forming the same (2025-12-23),
3. 12439594 - Semiconductor device and manufacturing method thereof (2025-10-07),
4. 12389672 - Method to embed planar FETs with finFETs (2025-08-12),
5. 12322715 - Method of forming integrated chip structure having slotted bond pad in stacked wafer structure (2025-06-03),
6. 12255133 - Electrical fuse (e-fuse) one-time programmable (OTP) device and manufacturing method thereof (2025-03-18),
7. 12127399 - Array boundary structure to reduce dishing (2024-10-22),
8. 12096621 - Multi-type high voltage devices fabrication for embedded memory (2024-09-17),
9. 12058856 - Semiconductor device and manufacturing method thereof (2024-08-06),
10. 12015029 - Method to embed planar FETs with finFETs (2024-06-18),
11. 11830875 - Method to embed planar FETS with FINFETS (2023-11-28),
12. 11825651 - Semiconductor device and manufacturing method thereof (2023-11-21),
13. 11758721 - Semiconductor device and manufacturing method thereof (2023-09-12),
14. 11742348 - Semiconductor device and method for forming the same (2023-08-29),
15. 11706914 - Method of forming an array boundary structure to reduce dishing (2023-07-18),

Title: The Innovative Journey of Inventor Li-Feng Teng

Introduction: Li-Feng Teng, a pioneering inventor hailing from Hsinchu, Taiwan, has made significant contributions to the world of technology and innovation through his groundbreaking inventions and patents.

Latest Patents: Li-Feng Teng holds several recent patents in the field of semiconductor technology, including a cutting-edge method for enhancing the efficiency of solar cells and a novel approach to improving the performance of integrated circuits.

Career Highlights: With a career spanning over two decades, Li-Feng Teng has established himself as a leading figure in the tech industry. He has worked with renowned companies and research institutions, playing a key role in the development of next-generation technologies.

Collaborations: Throughout his career, Li-Feng Teng has collaborated with top engineers, scientists, and researchers from around the globe. His collaborative efforts have led to the successful implementation of innovative solutions in various technological domains.

Conclusion: Li-Feng Teng's relentless pursuit of innovation and his passion for pushing the boundaries of technology have cemented his reputation as a visionary inventor. His contributions continue to inspire the next generation of inventors and shape the future of the tech industry.

Profile summary based on public USPTO records.
Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]
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