The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 07, 2025

Filed:

Jul. 05, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Wei-Cheng Wu, Zhubei, TW;

Li-Feng Teng, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10B 41/42 (2023.01); H10B 41/30 (2023.01); H10B 41/35 (2023.01); H10B 41/44 (2023.01); H10B 41/47 (2023.01); H10B 41/48 (2023.01); H10B 43/30 (2023.01); H10D 30/68 (2025.01); H10D 30/69 (2025.01); H10D 64/01 (2025.01);
U.S. Cl.
CPC ...
H10B 41/42 (2023.02); H10B 41/30 (2023.02); H10B 41/35 (2023.02); H10B 41/44 (2023.02); H10B 41/47 (2023.02); H10B 41/48 (2023.02); H10B 43/30 (2023.02); H10D 30/6892 (2025.01); H10D 30/696 (2025.01); H10D 64/017 (2025.01); H10D 64/035 (2025.01);
Abstract

A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer, and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.


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