The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 12, 2023
Filed:
Mar. 15, 2021
Applicant:
Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;
Inventors:
Wei Cheng Wu, Zhubei, TW;
Li-Feng Teng, Hsinchu, TW;
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/42 (2023.01); H01L 29/66 (2006.01); H01L 21/28 (2006.01); H10B 41/00 (2023.01); H10B 41/20 (2023.01); H10B 41/30 (2023.01); H10B 41/40 (2023.01); H10B 41/44 (2023.01); H10B 41/46 (2023.01); H10B 41/50 (2023.01); H10B 69/00 (2023.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H10B 41/42 (2023.02); H01L 29/40114 (2019.08); H01L 29/42328 (2013.01); H01L 29/66545 (2013.01); H01L 29/66825 (2013.01); H10B 41/00 (2023.02); H10B 41/20 (2023.02); H10B 41/30 (2023.02); H10B 41/40 (2023.02); H10B 41/44 (2023.02); H10B 41/46 (2023.02); H10B 41/50 (2023.02); H10B 69/00 (2023.02);
Abstract
A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate. A second dielectric layer is disposed between the floating gate and the control gate, having one of a silicon nitride layer, a silicon oxide layer and multilayers thereof. A third dielectric layer is disposed between the second dielectric layer and the control gate, and includes a dielectric material having a dielectric constant higher than silicon nitride.