The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 12, 2025

Filed:

May. 09, 2024
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Harry-Hak-Lay Chuang, Zhubei, TW;

Wei Cheng Wu, Zhubei, TW;

Li-Feng Teng, Hsinchu, TW;

Li-Jung Liu, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10D 84/83 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01);
U.S. Cl.
CPC ...
H10D 84/834 (2025.01); H10D 30/6219 (2025.01); H10D 62/115 (2025.01);
Abstract

Various embodiments of the present disclosure are directed towards a method to embed planar field-effect transistor (FETs) with fin field-effect transistors (finFETs). A semiconductor substrate is patterned to define a mesa and a fin. A trench isolation structure is formed overlying the semiconductor substrate and surrounding the mesa and the fin. A first gate dielectric layer is formed on the mesa, but not the fin. The trench isolation structure recessed around the fin, but not the mesa, after the forming the first gate dielectric layer. A second gate dielectric layer is deposited overlying the first gate dielectric layer at the mesa and further overlying the fin. A first gate electrode is formed overlying the first and second gate dielectric layers at the mesa and partially defining a planar FET. A second gate electrode is formed overlying the second gate dielectric layer at the fin and partially defining a finFET.


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