Lawrence Loh

This inventor holds 18 USPTO granted patents, primarily in Electronic Design Verification. Top assignees: Jasper Design Automation, Inc., Cadence Design Systems, Inc.. Active years: 2007-2019.

IDiyas Innovation Intelligence. (2026). Inventor Profile: Lawrence Loh. Retrieved from https://idiyas.com/inventor/lawrence-loh

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Calculating rank

USPTO Granted Patents = 18

% Patents Active = 94.4

Average Co-Inventor Count = 3.9

ph-index = 9

Forward Citations = 195(Granted Patents)

Company Filing History:

12 out of 34

Jasper Design Automation, Inc.

patents

6 out of 2,620

Cadence Design Systems, Inc.

patents

Years Active: 2007-2019

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Areas of Expertise:

Electronic Design

Verification Techniques

Clock Domain Crossing

Security Data Path

Formal Verification

Low Power Functionality

Equivalency Checks

Design Efficiency

RTL Transformation

Hierarchical Verification

Counter Management

Complexity Management

18 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10204201 - Methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniques (2019-02-12),

2. 9934410 - Security data path verification (2018-04-03),

3. 9922209 - Security data path verification (2018-03-20),

4. 9633153 - Method, system, and computer program product for verifying an electronic design using stall prevention requirements of electronic circuit design models of the electronic design (2017-04-25),

5. 9633151 - Methods, systems, and computer program product for verifying electronic designs with clock domain crossing paths (2017-04-25),

6. 9594861 - Method and system to perform equivalency checks (2017-03-14),

7. 9449196 - Security data path verification (2016-09-20),

8. 9104824 - Power aware retention flop list analysis and modification (2015-08-11),

9. 8954904 - Veryifing low power functionality through RTL transformation (2015-02-10),

10. 8863049 - Constraining traces in formal verification (2014-10-14),

11. 8831925 - Indexing behaviors and recipes of a circuit design (2014-09-09),

12. 8731894 - Indexing behaviors and recipes of a circuit design (2014-05-20),

13. 8381148 - Formal verification of deadlock property (2013-02-19),

14. 7647572 - Managing formal verification complexity of designs with multiple related counters (2010-01-12),

15. 7437694 - System and method for determining and identifying signals that are relevantly determined by a selected signal in a circuit design (2008-10-14),

Title: The Innovations of Lawrence Loh

Introduction

Lawrence Loh is a prominent inventor based in Milpitas, California, known for his significant contributions to electronic design verification. With a total of 18 patents to his name, Loh has developed innovative techniques that enhance the reliability and security of electronic systems.

Latest Patents

Among his latest patents, Loh has introduced methods, systems, and articles of manufacture for verifying an electronic design using hierarchical clock domain crossing verification techniques. These techniques focus on identifying an electronic design that includes a top hierarchy and one or more instances at a first child hierarchy below the top hierarchy. The design can be decomposed into a top hierarchy block and one or more child blocks, allowing for the generation of a plurality of data structures through separate processing on various computing nodes. Additionally, he has developed a security data path verification system that employs a formal verification approach to ensure data access and propagation paths in circuit designs are secure. This system proves the unreachability of path cover properties, thereby enhancing the integrity of circuit designs.

Career Highlights

Loh has worked with notable companies in the field, including Jasper Design Automation, Inc. and Cadence Design Systems, Inc. His experience in these organizations has allowed him to refine his skills and contribute to groundbreaking advancements in electronic design.

Collaborations

Throughout his career, Loh has collaborated with esteemed colleagues such as Chung-Wah Norris Ip and Howard Wong-Toi. These partnerships have fostered an environment of innovation and creativity, leading to the development of impactful technologies.

Conclusion

Lawrence Loh's work in electronic design verification has made a significant impact on the industry. His innovative patents and collaborations highlight his dedication to advancing technology and ensuring the security of electronic systems.

Profile summary based on public USPTO records.

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]