The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 12, 2019
Filed:
Jun. 30, 2016
Cadence Design Systems, Inc., San Jose, CA (US);
Lawrence Loh, Milpitas, CA (US);
Artur Melo Mota Costa, Belo Horizonte, BR;
Breno Rodrigues Guimaraes, Belo Horizonte, BR;
Fabiano Peixoto, Belo Horizonte, BR;
Andrea Iabrudi Tavares, Belo Horizonte, BR;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Disclosed are techniques for verifying an electronic design using hierarchical clock domain crossing verification techniques. These techniques identify an electronic design including a top hierarchy and one or more instances at a first child hierarchy below the top hierarchy. The electronic design may be decomposed into a top hierarchy block for the top hierarchy and one or more child blocks for the one or more instances. A plurality of data structures may be generated by separately processing the top hierarchy block and the one or more child blocks on one or more computing nodes. One or more clock domain crossing structures may be identified in the electronic design at least by integrating the plurality of data structures.