The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2014
Filed:
Dec. 06, 2010
Lars Lundgren, Gothenburg, SE;
Ziyad Hanna, Haifa, IL;
Chung-wah Norris Ip, Cupertino, CA (US);
Kathryn Drews Kranen, Menlo Park, CA (US);
Lawrence Loh, Milpitas, CA (US);
Lars Lundgren, Gothenburg, SE;
Ziyad Hanna, Haifa, IL;
Chung-Wah Norris Ip, Cupertino, CA (US);
Kathryn Drews Kranen, Menlo Park, CA (US);
Lawrence Loh, Milpitas, CA (US);
Jasper Design Automation, Inc., Mountain View, CA (US);
Abstract
The result of a property based formal verification analysis of a circuit design may include at least one counterexample for each property that is violated, which a user can use to debug the circuit design. To assist the user in this debugging process, a debugging tool applies one or more soft constraints to a counterexample trace that simplify the appearance of the trace when displayed as a waveform. The debugging tool thus facilitates a user's understanding of what parts of the counterexample trace are responsible for the property failure. Also described is a power analysis tool that increases the noise level of a trace for a circuit design in order to facilitate analysis of the circuit design's power characteristics.