Company Filing History:

18 out of 34

Jasper Design Automation, Inc.

patents

12 out of 2,542

Cadence Design Systems, Inc.

patents

Years Active: 2005-2020

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30 patents (USPTO):Sort by Forward CitationsExplore Patents

1. 10783304 - System, method, and computer program product for displaying debugging during a formal verification (2020-09-22),

2. 10635768 - System, method, and computer program product for displaying multiple traces while debugging during a formal verification (2020-04-28),

3. 10409945 - Methods, systems, and computer program product for connectivity verification of electronic designs (2019-09-10),

4. 10380295 - Methods, systems, and articles of manufacture for X-behavior verification of an electronic design (2019-08-13),

5. 10331547 - System, method, and computer program product for capture and reuse in a debug workspace (2019-06-25),

6. 10162917 - Method and system for implementing selective transformation for low power verification (2018-12-25),

7. 10094875 - Methods, systems, and articles of manufacture for graph-driven verification and debugging of an electronic design (2018-10-09),

8. 9928328 - Method and system for automated debugging of a device under test (2018-03-27),

9. 9734278 - Methods, systems, and articles of manufacture for automatic extraction of connectivity information for implementation of electronic designs (2017-08-15),

10. 9659142 - Methods, systems, and articles of manufacture for trace warping for electronic designs (2017-05-23),

11. 9477802 - Isolating differences between revisions of a circuit design (2016-10-25),

12. 9081927 - Manipulation of traces for debugging a circuit design (2015-07-14),

13. 8990745 - Manipulation of traces for debugging behaviors of a circuit design (2015-03-24),

14. 8984461 - Visualization constraints for circuit designs (2015-03-17),

15. 8863049 - Constraining traces in formal verification (2014-10-14),

Title: Chung-Wah Norris Ip: Innovator in Electronic Design Verification

Introduction

Chung-Wah Norris Ip, based in Cupertino, CA, is a prominent inventor with an impressive portfolio of 30 patents. His work primarily focuses on electronic design automation and formal verification, contributing significantly to advancements in the field.

Latest Patents

Among his latest patents is the "System, method, and computer program product for displaying debugging during a formal verification." This innovation relates to a method for electronic design, where the user can analyze cover traces or assertion counter-examples through a graphical user interface during debugging sessions. The method also allows for the identification of dead-end states and the conversion of constraints to soft constraints, enhancing the debugging process. Another notable patent is the "System, method, and computer program product for displaying multiple traces while debugging during a formal verification." This invention involves generating and displaying multiple traces associated with formal verification, allowing users to select from various traces for analysis while performing verification tasks.

Career Highlights

Chung-Wah Norris Ip has made significant contributions during his tenure at esteemed companies such as Jasper Design Automation, Inc. and Cadence Design Systems, Inc. His innovations have played a crucial role in enhancing the reliability and efficiency of electronic designs.

Collaborations

Throughout his career, Chung-Wah has collaborated with notable professionals—including Lawrence Loh and Kathryn Drews Kranen—fostering a productive environment that encourages innovation within the field of electronic design automation.

Conclusion

Chung-Wah Norris Ip continues to make strides in the electronic design industry through his innovative patents and collaborative efforts. His dedication to advancing formal verification techniques not only highlights his expertise but also reinforces his status as a leading inventor in the field. As he progresses, the impact of his work will likely resonate throughout the industry and inspire future innovations.

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