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Mountain View, CA, United States of America

Jasper Design Automation, Inc.

USPTO Granted Patents = 34

% Expired Patents = 11.8

Trademarks = 1

Forward Citations = 459

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37 inventors (with patents filed for the assignee):

Chung-Wah Norris Ip (18 out of 30 patents)

Lawrence Loh (12 out of 18 patents)

Vigyan Singhal (9 out of 14 patents)

4. Rajeev Kumar Ranjan (6 out of 10 patents)

5. Kathryn Drews Kranen (6 out of 8 patents)

6. Howard Wong-Toi (6 out of 6 patents)

7. Yann Alain Antonioli (5 out of 5 patents)

8. Craig Franklin Deaton (4 out of 10 patents)

9. Ziyad Hanna (4 out of 18 patents)

10. Joseph E Higgins (4 out of 5 patents)

11. Chien-Liang Lin (3 out of 7 patents)

12. Beth C Isaksen (3 out of 4 patents)

13. Asa Ben-Tzur (3 out of 3 patents)

14. Soe Myint (3 out of 4 patents)

15. Claudionor José Nunes Coelho (3 out of 3 patents)

Core Competencies:

Functional Property Ranking

Security Data Path Verification

Power Aware Retention Flop

Circuit Design Debugging

Formal Verification

Trace Signatures

Waveform Comprehension

Design Efficiency Parameters

Visualization Constraints

Counterexample Debugging

Signal Relevance Identification

Design Navigation

34 patents: Sort by Forward Citations

1. 9460252 - Functional property ranking (2016-10-04),

2. 9449196 - Security data path verification (2016-09-20),

3. 9104824 - Power aware retention flop list analysis and modification (2015-08-11),

4. 9081927 - Manipulation of traces for debugging a circuit design (2015-07-14),

5. 8990745 - Manipulation of traces for debugging behaviors of a circuit design (2015-03-24),

6. 8984461 - Visualization constraints for circuit designs (2015-03-17),

7. 8954904 - Veryifing low power functionality through RTL transformation (2015-02-10),

8. 8863049 - Constraining traces in formal verification (2014-10-14),

9. 8831925 - Indexing behaviors and recipes of a circuit design (2014-09-09),

10. 8826201 - Formal verification coverage metrics for circuit design properties (2014-09-02),

11. 8739092 - Functional property ranking (2014-05-27),

12. 8731894 - Indexing behaviors and recipes of a circuit design (2014-05-20),

13. 8671373 - Analysis of circuit designs via trace signatures (2014-03-11),

14. 8630824 - Comprehending waveforms of a circuit design (2014-01-14),

15. 8572527 - Generating properties for circuit designs (2013-10-29),

Company Overview

Jasper Design Automation, Inc. is a technology company based in Mountain View, California, specializing in electronic design automation (EDA) solutions. The company focuses on developing advanced software tools that enhance the design and verification processes for integrated circuits and systems on chips. By leveraging innovative methodologies, Jasper aims to improve design efficiency and accuracy, catering to the needs of semiconductor companies and electronic engineers in a rapidly evolving technological landscape.

Profile summary synthesized from public USPTO records and patent filings.

Company Badge

USPTO Data Jan 1 1976 - Oct 6 2026

34 Patents

#92 in Mountain View, CA

#2,377 in California

#10,002 in US

#19,612 in the World

Mountain View, CA, United States of America

Jasper Design Automation, Inc.

Forward Citations = 459

37 inventors:

Chung-Wah Norris Ip (18 out of 30 patents)

Lawrence Loh (12 out of 18 patents)

Vigyan Singhal (9 out of 14 patents)

4. Rajeev Kumar Ranjan (6 out of 10 patents)

5. Kathryn Drews Kranen (6 out of 8 patents)

IDiyas Innovation Intelligence. (2026). Company Patent Portfolio: Jasper Design Automation, Inc.. Retrieved from https://idiyas.com/company/jasper-design-automation

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

Data Sources: USPTO Patent Grant XML, Patent Center, EPO & CIPO • Normalized by IDiyas Innovation Graph. Methodology & provenance architecturePlease report any incorrect information to [email protected]

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